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Registered: ‎11-09-2015

Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP

Introduction

 

 

This Video Beginner Series 8 gives you tips to debug the AXI4-Stream to Video Out IP with various labs as examples.

 

 

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

 

Summary

 

1. Common issues using the AXI4-Stream to Video Out IP
2. Labs - Debugging the AXI4-Stream to Video Out

3. What Next?

 

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP - Common issues using the AXI4-Stream to Video Out IP

Common issues using the AXI4-Stream to Video Out IP

 

 

When the locked output of the AXI4-Stream to Video Out IP is not getting high, it is mainly due to the following root causes

  • The input stream too slow for the timing signals
  • There is a mismatch between the size of the input stream and the timing signals
  • There is no data coming on the input stream

 

Input Stream too slow or for the timing signals

 

When the Input Stream is too slow for the timing signals, the internal FIFO might under-flow. This can be seen when the underflow output from the IP is high. One common solution is to use a VDMA or a Video Frame Buffer before the AXI4-Stream to Video Out IP. This can sometimes also be solved by increasing the frequency of the input stream when possible.

 

 

Mismatch between the size of the input stream and the timing signals

 

The AXI4-Stream to Video Out IP is checking that the size of the input stream and the size of the timing signals match. If not, it will not lock. This issue can be detected on the status output, in particular the bits [3:6]:

 

  • If bit 3 is ‘1’, it indicates VTG EOL (End Of Line) Leading. This means that the EOL signal (hsync) from the Video Timing Generator happens before the EOL signal from the AXI4-Stream (tlast). In other words, the horizontal size configured in the VTG is smaller than the horizontal size coming on the AXI4-Interface

  • If bit 4 is ‘1’, it indicates VTG EOL Lagging. This means that the EOL signal (hsync) from the Video Timing Generator happens after the EOL signal from the AXI4-Stream (tlast). In other words, the horizontal size configured in the VTG is bigger than the horizontal size coming on the AXI4-Interface

  • If bit 5 is ‘1’, it indicates VTG SOF (Start Of Frame) Leading. This means that the SOF signal (vsync) from the Video Timing Generator happens before the SOF signal from the AXI4-Stream (tuser). In other words, the vertical size configured in the VTG is smaller than the vertical size coming on the AXI4-Interface

  • If bit 6 is ‘1’, it indicates VTG SOF Lagging. This means that the SOF signal (vsync) from the Video Timing Generator happens after the SOF signal from the AXI4-Stream (tuser). In other words, the vertical size configured in the VTG is bigger than the vertical size coming on the AXI4-Interface

No data coming on the input stream

 

When no data is coming on the AXI4-Stream interface, it can usually be detected by 2 indicators: the underflow signals will be high and the tvalid input will stay low while the tready output is high.

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP - Labs

Labs - Debugging the AXI4-Stream to Video Out

 

Note 1: This tutorial is intended to be used only with Vivado 2018.1 and only in simulation

Note 2: A valid license for the Test Pattern Generator is required to build the designs.

 

  1. Download the tutorial files and unzip the folder

Lab1

 

  1. Open Vivado 2018.1

  2. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0008)

  3. In the tcl console, source the script create_lab1.tcl (source ./create_lab1.tcl)

  4. Run the simulation for 150ms

  5. We can see that the underflow signal is toggling (high for some times) and the AXI4-Stream to Video out IP is not getting locked

    1.png
    Q1. What does this indicate about the data stream?

  1. Close the simulation

  2. Open the test bench file tb_AXI4S_to_Vid_Out.sv in the Vivado text editor

  3. Find the lines defining the clock periods

 

// Generate the clocks
//12.5ns (1/2 period) -> 40MHz clock
always #12.5ns vid_clk = ~vid_clk;
//16.6ns (1/2 period) -> ~30MHz clock
always #16.6ns stream_clk = ~stream_clk;

 

 

Q2. Knowing that the video clock (vid_clk) is fixed (depends on the resolution), what can you change to avoid the underflow and getting the AXI4-Stream to Video Out to lock?

Q3.Try to make a change in the test bench and run the simulation for 150ms. Make sure the AXI4-Stream is now locking.
2.png

  1. Close the simulation and the Vivado project

Lab 2

  1. In the tcl console, source the script create_lab2.tcl (source ./create_lab2.tcl)

  2. Run the simulation for 80ms

  3. We can see that the AXI4-Stream is not locking and that the vtg_ce signals stays low

 3.png

 

Q4. What do observe you on the underflow output?

Q5.What are the state of the AXI4-Stream?

Q6. What could be the issue here?

 

  1. Close the simulation
  2. Open the test bench file tb_AXI4S_to_Vid_Out.sv in the Vivado text editor

    Q7. What is the error in the test bench file? (tip: look at line 167)

    Q8. Fix the issue and re-launch the simulation
  1. Run the simulation for 150ms.

  2. Verify that the AXI4-Stream to Video Out IP is locking
    4.png
  1. Close the simulation and the Vivado project

Lab 3

  1. In the tcl console, source the script create_lab3.tcl (source ./create_lab3.tcl)

  2. Run the simulation for 150ms

  3. We can see that the AXI4-Stream to Video Out IP is not locking and that the bit 5 of the status output is high
    5.png
    Q9. What does a ‘1’ on the bit 5 of status output indicates?

    Q10. What can be the error in this design?
  1. Close the simulation
  2. Open the block design AXI4S_to_Vid_Out_bd_i.

  3. Double click on the Video Timing Controller IP to open its configuration GUI.

  4. In the VTC IP GUI, select the Default/Constant page and find the horizontal and vertical sizes settings
    6.png

 

  1. Close the VTC GUI by clicking on Cancel
  2. Open the test bench file tb_AXI4S_to_Vid_Out.sv in the Vivado text editor

  3. Find the line for the TPG configuration

 

/////////////////////////////////////////////////////////////////
// TPG Configuration
integer height=650, width=800;
/////////////////////////////////////////////////////////////////

 

 

Q11. What is the issue here?

Q12. Fix the issue and re-launch the simulation

 

  1. Run the simulation for 150ms.

  2. Verify that the AXI4-Stream to Video Out IP is locking

  3. Close Vivado



Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP - What Next?

What Next?

 

 

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