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Observer tmiller
Observer
874 Views
Registered: ‎10-24-2017

Video PHY reference clock

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Hello,

 

I am currently trying to add two DisplayPort transmitters to an existing FPGA design (xcku040-ffva1156). The transmitters will each use the DP TX subsystem (v2.0) and the Video PHY controller (v2.0). Both transmitters will sit in the same bank, with a line rate of 2.7 Gbps and identical video timings. The bank is currently provided with a single 156.25MHz external reference clock. I have two questions:

 

1) Is 156.25 MHz an acceptable frequency? I have used the DisplayPort IP v7.0 before, and the documentation specifies that a 270 MHz reference clock is required for all line rates. I'm not so familiar with the Video PHY, but I suspect the same applies. I can't see any information in the documentation. 

 

2) Can two Video PHYs within the same bank share the same reference clock?

 

https://japan.xilinx.com/support/documentation/ip_documentation/displayport/v7_0/pg064-displayport.pdf 

https://www.xilinx.com/support/documentation/ip_documentation/vid_phy_controller/v2_0/pg230-vid-phy-controller.pdf

https://www.xilinx.com/support/documentation/ip_documentation/dp_tx_subsystem/v2_0/pg199-displayport-tx-subsystem.pdf

 

Thank you for any help.

 

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Moderator
Moderator
1,124 Views
Registered: ‎11-09-2015

Re: Video PHY reference clock

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HI @tmiller,

 

1) Is 156.25 MHz an acceptable frequency? I have used the DisplayPort IP v7.0 before, and the documentation specifies that a 270 MHz reference clock is required for all line rates. I'm not so familiar with the Video PHY, but I suspect the same applies. I can't see any information in the documentation. 

-> I am quite sure the same rules apply (the DP subsystem includes the DP IP), so I think you need to use 270. I will ask for more clarification in the new documentation

 

2) Can two Video PHYs within the same bank share the same reference clock?

-> I would say yes if they in adjacent QUADs and if they don't to support different resolutions

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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1 Reply
Moderator
Moderator
1,125 Views
Registered: ‎11-09-2015

Re: Video PHY reference clock

Jump to solution

HI @tmiller,

 

1) Is 156.25 MHz an acceptable frequency? I have used the DisplayPort IP v7.0 before, and the documentation specifies that a 270 MHz reference clock is required for all line rates. I'm not so familiar with the Video PHY, but I suspect the same applies. I can't see any information in the documentation. 

-> I am quite sure the same rules apply (the DP subsystem includes the DP IP), so I think you need to use 270. I will ask for more clarification in the new documentation

 

2) Can two Video PHYs within the same bank share the same reference clock?

-> I would say yes if they in adjacent QUADs and if they don't to support different resolutions

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos