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2,420 Views
Registered: ‎02-15-2018

Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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HI There,

I noticed that in the example designs and application notes, the vpss integrated de-interlacer is listed as supporting 1080i only. 

Specifically XAPP1291 v1.01 describes support for 1080i only. " Interlaced input support: 1080i only"

In xv_deinterlacer_l2.h , in the comment header it states   * Currently only 1080i input is supported

 

I entered a design with a Fully Fledged core with deinterlacer (Motion Adaptive disabled).  I find that 1080i does deinterlace but 480i generates no output when the size is set for 480i as follows:

 

XSys_SetStreamParam(VpssPtr, XSYS_VPSS_STREAM_IN, 720, 240, 60, XVIDC_CSF_YCRCB_444, TRUE );

 

Is this a limitation of the deinerlacer subcore (1080i support only)

The deinterlacer subcore that I am evaluating is Version 5 Rev 8 within vprocss 2.4 (with Vivado 2017.3)

 

If only 1080i is supported, would the V4 standalone legacy core de-interlacer work for 480i?

 

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2,100 Views
Registered: ‎02-15-2018

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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Thanks Florent,

I found the problem.

I had a chroma resampler (4.0) placed before the video processing subsystem block and it was preset to 1920 x 1080 resolution and no axi-lite register interface to allow changes to the resolution. Consequently, when SD interlaced video was applied, it was not passing through properly from the chroma resampler to the vprocss block.

I changed the design by removing the 4:2:2 to 4:4:4 chroma resampler and instead using the one that is integrated within the vprocss and it is working now.

Thanks to you and Reaiken for the suggestions.

10 Replies
Moderator
Moderator
2,392 Views
Registered: ‎11-09-2015

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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Hi @killianosullivan,

 

The VPSS should work with other resolution than 1080i. The example design should be doing 480i. Did you try to start with it to have an example for you application? Did you check the log for the VPSS?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
2,379 Views
Registered: ‎02-15-2018

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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Thanks Florent,

Thats at least good to know that 480i is supported.

 

I currently get a frozen image suggesting that the deinterlacer processed the 1st field at startup. If I restart the core, it updates the frozen frame.

 

How or where do I access the  log for the VPSS?

 

I have output status reports on the VPSS to teh console and have pasted below:

 

 


----->Deinterlacer IP STATUS<----
IsDone: 0
IsIdle: 0
IsReady: 0
Ctrl: 0x81

Read Frame Buffer: 0x0
Write Frame Buffer: 0x0
Color Format: 1
Algo Selected: 0
Width : 720
Height : 240


----->V SCALER IP STATUS<----
IsDone: 0
IsIdle: 0
IsReady: 0
Ctrl: 0x81

Scaler Type: Bicubic
Input Width: 720
Input Height: 480
Output Height: 720
4:2:0 processing: Disabled
Color Format: YUV_444
Line Rate: 43690
Num Phases: 64


----->H SCALER IP STATUS<----
IsDone: 1
IsIdle: 0
IsReady: 0
Ctrl: 0x81

Scaler Type: Bicubic
Input&Output Height: 720
Input Width: 720
Output Width: 1280

4:2:2 processing: Disabled
4:2:0 processing: Disabled
Color space conversion: Disabled
Input Color Format: YUV_444
Output Color Format: YUV_444
Pixel Rate: 36864

Num Phases: 64

------ SUBSYSTEM INPUT/OUTPUT CONFIG ------
->INPUT
Color Format: YUV_444
Color Depth: 8
Pixels Per Clock: 1
Mode: Interlaced
Frame Rate: 60Hz
Resolution: 720x480@60Hz (I)
Pixel Clock: 13513500

->OUTPUT
Color Format: YUV_444
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 1280x720@60Hz
Pixel Clock: 74250000

Zoom Mode: OFF

Pip Mode: OFF

Data Flow Map: VidIn -> DEINT -> VDMA -> SCALER-V -> SCALER-H -> LBOX -> CSC -> VidOut

 

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2,372 Views
Registered: ‎02-15-2018

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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Just worth reiterating that 1080i sources do deinterlace when I apply a 1080i source and set the input stream parameter to:

XSys_SetStreamParam(VpssPtr, XSYS_VPSS_STREAM_IN, 1920, 540, 60, XVIDC_CSF_YCRCB_444, TRUE );

 

But when I change the source to 480i and set the input stream parameter to:

XSys_SetStreamParam(VpssPtr, XSYS_VPSS_STREAM_IN, 720, 240, 60, XVIDC_CSF_YCRCB_444, TRUE );

 

The output is frozen frame store contents from the VDMA inside the vprocss.

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Explorer
Explorer
2,358 Views
Registered: ‎07-18-2011

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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@killianosullivan wrote:

Just worth reiterating that 1080i sources do deinterlace when I apply a 1080i source and set the input stream parameter to:

XSys_SetStreamParam(VpssPtr, XSYS_VPSS_STREAM_IN, 1920, 540, 60, XVIDC_CSF_YCRCB_444, TRUE );

 

But when I change the source to 480i and set the input stream parameter to:

XSys_SetStreamParam(VpssPtr, XSYS_VPSS_STREAM_IN, 720, 240, 60, XVIDC_CSF_YCRCB_444, TRUE );

 


 

480i60 (BT.656 related) and 1080i60 (BT.1120 related) sources are normally 4:2:2 Y/CbCr, not 4:4:4 Y/Cb/Cr.   I don't know if you have a chroma resampler in the path or not, but it may not work properly if they are indeed 4:2:2 sources.    If that is the case, you might try setting your stream parameters to XVIDC_CSF_YCRCB_422.

 

 

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2,356 Views
Registered: ‎02-15-2018

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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Thanks for the quick reply.

I do have a an external chroma interpolator before the vpss to convert from 4:2:2 YCbCr to  4:4:4 YCbCr.

That is verified by the fact that 1080i works coming in on the same video path from an external generator.

 

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Explorer
Explorer
2,338 Views
Registered: ‎07-18-2011

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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Okay, I just made a design with a full-fledged scaler using motion-adaptive deinterlacing and VDMA in an Artix7 XC7A100T-2FGG484I device, and it appears to work at both 1080i60 and 480i60 in and 1400x1050 SXGA++ out (the native resolution of the LCD I am driving), using the XVIDC_CSF_YCRCB_422 format, but I am using a TPG IP block as the video source, and have the deint_field_id tied low, so it isn't a true real-life test.

 

I have an NTSC decoder on the board, I'll try to hook it up next and generate a real-world 480i60 with field id.

 

To see the Vproc subystem reports for your design, add these lines to your code, substituting the address of your XVprocSs scaler instance in place of "Vproc_InScaler":

 

    xil_printf("\r\nVPSS report info\r");
    VprocSs_ReportInfo(&Vproc_InScaler);

 

You should get something like this in the SDK terminal window, if you have an AXI-Lite UART in your design:

 

 

VPSS report info
****Reporting System Design Info****

****** Video Processing Subsystem Configuration ******

Topology: Full-Fledged

  ->Sub-Cores Included

    : Horiz. Chroma Resampler
    : H Scaler
    : V Scaler
    : VDMA
    : LetterBox
    : Color Space Converter
    : Deinterlacer
    : Reset (AXIS)
    : Reset (AXI-MM)
    : AXIS Router

Pixels/Clk  = 2
Color Depth = 8
Num Video Components = 3
Max Width Supported  = 2048
Max Height Supported = 2048

----->CSC IP STATUS<----

IsDone:           1
IsIdle:           0
IsReady:          0
Ctrl:             0x81

4:2:2 processing: Enabled
4:2:0 processing: Disabled
Color Format In:  YUV_422
Color Format Out: YUV_422
Active Width:     1400
Active Height:    1050

Demo Window:      Disabled
Column Start:     0
Column End:       1399
Row Start:        0
Row End:          1049

Global Window:

R Offset:         1
G Offset:         0
B Offset:         0
Min Clamp:        0
Max Clamp:        255

Coefficients:

 r0:  4092    -1    -6
 r1:     1  4095     2
 r2:     1     0  4085

Demo Window is the Global Window.

----->H Chroma Resampler IP STATUS<----

IsDone:  0
IsIdle:  1
IsReady: 1
Ctrl:    0x4

Resampling Type:  FIR
Video Format In:  RGB
Video Format Out: RGB
Width:            0
Height:           0
Num Taps:         4

Coefficients:

Phase  0:    0    0    0    0
Phase  1:    0    0    0    0

----->H SCALER IP STATUS<----

IsDone:  1
IsIdle:  0
IsReady: 0
Ctrl:    0x81

Scaler Type:        Polyphase
Input&Output Height:    1050
Input Width:            720
Output Width:           1400
4:2:2 processing:       Enabled
4:2:0 processing:       Disabled
Color space conversion: Disabled
Input Color Format:     YUV_422
Output Color Format:    YUV_422
Pixel Rate:             33704
Num Phases:          64
Num Taps:            6

 


Coefficients:

Phase  0:  -132   236  3824   236  -132    64
...... ( a bunch of phase stuff deleted for brevity)
Phase 63:    64  -144   292  3816   184  -116

----->V SCALER IP STATUS<----

IsDone:  1
IsIdle:  0
IsReady: 0
Ctrl:    0x81

Scaler Type:     Polyphase
Input Width:      720
Input Height:     480
Output Height:    1050
4:2:0 processing: Disabled
Color Format:     YUV_422
Line Rate:        29959
Num Phases:       64
Num Taps:        6

Coefficients:

Phase  0:  -132   236  3824   236  -132    64

... ( a bunch of phase stuff deleted for brevity)
Phase 63:    64  -144   292  3816   184  -116

------ SUBSYSTEM INPUT/OUTPUT CONFIG ------

->INPUT

    Color Format:     YUV_422
    Color Depth:      8
    Pixels Per Clock: 2
    Mode:             Interlaced
    3D Format:        Frame Packing
    Frame Rate:       60Hz
    Resolution:       720x480@60Hz (I)
    Pixel Clock:      13513500

->OUTPUT

    Color Format:     YUV_422
    Color Depth:      8
    Pixels Per Clock: 2
    Mode:             Progressive
    3D Format:        Frame Packing
    Frame Rate:       60Hz
    Resolution:       1400x1050@60Hz
    Pixel Clock:      121793760


Zoom Mode: OFF
Pip  Mode: OFF
Data Flow Map: VidIn -> DEINT -> VDMA -> SCALER-V -> SCALER-H -> LBOX -> CSC -> VidOut

 

 

Explorer
Explorer
2,314 Views
Registered: ‎07-18-2011

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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Another thought - have you tried adding a TPG IP block instead of an external generator to use as a 480i source?   If there is a mismatch between the input 480i AXI4-stream and the VDMA resolution at 480i, it could cause the VDMA to stop, or the output to unlock.  

 

Do you have a VTC detecting the input timing from a Video In to AXI4-stream IP block?  If so, are you using the received timing values from that to configure the scaler, or are you just manually entering the expected numbers in your code?  The 480i from your generator might not be correct.

 

I find it is best to start with the bare minimum configuration running from a TPG and add IP blocks incrementally, compiling and debugging each one as I go along.  It takes a bit more time, but usually makes it easier to find mistakes in HW or SW setup.

2,310 Views
Registered: ‎02-15-2018

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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Reaiken,

Thanks for the considerable amount of info in your reply. I have been using an external 480i source but will switch in a TPG to see what happens.   Also, thanks for the tip in accessing the vpss log.

I am inclined to agree with your approach (with the benefit of hindsight) that building up from a bare bones configuration and incrementally add in the blocks is the safest way to go. 

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Moderator
Moderator
2,056 Views
Registered: ‎11-09-2015

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

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HI @killianosullivan,

 

Is everything clear for you on this subject? If yes, please kindly mark a reply as solution to close the topic.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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2,101 Views
Registered: ‎02-15-2018

Re: Video Processing Sub System 2s Deinterlacer support beyond 1080i only

Jump to solution

Thanks Florent,

I found the problem.

I had a chroma resampler (4.0) placed before the video processing subsystem block and it was preset to 1920 x 1080 resolution and no axi-lite register interface to allow changes to the resolution. Consequently, when SD interlaced video was applied, it was not passing through properly from the chroma resampler to the vprocss block.

I changed the design by removing the 4:2:2 to 4:4:4 chroma resampler and instead using the one that is integrated within the vprocss and it is working now.

Thanks to you and Reaiken for the suggestions.