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Observer rleopold
Observer
8,573 Views
Registered: ‎04-30-2014

Video Processing Subsystem 2.0 - Deinterlacer Only

Curious if anyone has gotten this to work.  I am feeding 1080i into a Video In to AXI4-Stream IP block and then to the VPSS/Deinterlacer IP block.  The Video In to AXI4-Streaming IP is configured as 2 Pixels per Clock, Video Format = YUV 4:2:2, video in = 8 bits, video out = 8 bits, FIFO depth = 1024, Independent Clocks.  The VPSS is configured for Deinterlacer Only, 2 Samples per Clock, 8 bits, Maximum number of Pixels is 1920, Maximum number of lines is 1080.  Motion Adaptive Deinterlacing is disabled (no external memory interface).  I am feeding the Video In to AXI4-Streaming IP block 1080i 4:2:2, 2samples per clock video.  I set the registers in the VPSS/DEI as follows:  offset 0x30 (Color Format) = 2, Offset 0x10 (Width) = 0x780 (1920), offset 0x18 (Height) = 0x438 (1080).  I set offset 0x0 to 0x80 and then to 0x1 per the example driver.  Out of the VPSS tready starts off high but when I feed it video it stays high for one frame and then goes low and stays low.  My AXIS clock is 200MHz.  FPGA is a Kintex 7.  "m_axis_tready" feeding the output of the VPSS/DEI is tied high so it's aways ready for data.  Any thoughts?

VPSS_DEI_1.PNG
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6 Replies
Xilinx Employee
Xilinx Employee
8,505 Views
Registered: ‎08-02-2011

Re: Video Processing Subsystem 2.0 - Deinterlacer Only

Hello,

 

First thing I would say is that you really should use the v_proc driver instead of doing direct register writes. The core is designed to be used with the driver because it is a very flexible and dynamic subsystem (comprised of many sub IPs that need to work in harmony) so the driver is needed to manage complexity. In fact, officially the VPSS is only supported if the driver is used.

 

Also, what's up with tstrb? Strange that it's toggling like that... What's driving that?

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Xilinx Employee
Xilinx Employee
8,477 Views
Registered: ‎07-31-2012

Re: Video Processing Subsystem 2.0 - Deinterlacer Only

 

• Check that the aclk inputs are connected and toggling.
• Check that the AXI4-Stream waveforms are being followed.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Observer rleopold
Observer
8,454 Views
Registered: ‎04-30-2014

Re: Video Processing Subsystem 2.0 - Deinterlacer Only

Eventually we will use the driver.  Our design has the processor external to the FPGA and a seperate person is working that.  We've done this same thing with other VPSS designs using the Scaler.  We ran teh driver code and looked at what it generates and I am replicating that.

 

I think tstrb is actually tvalid in that picture.  Probably because the video is at 74.25MHz and teh AXIS clock is at 200MHz tvalid must toggle.

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Visitor yweehong
Visitor
3,146 Views
Registered: ‎09-19-2013

Re: Video Processing Subsystem 2.0 - Deinterlacer Only

Hi,

 

  I am seeing the same problem with my project.

 

  I have to set the registers directly as there are no petalinux drivers available for the VPSS yet. 

 

  Did the original poster or anyone managed to resolve this?

 

 

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Xilinx Employee
Xilinx Employee
3,044 Views
Registered: ‎07-31-2012

Re: Video Processing Subsystem 2.0 - Deinterlacer Only

Which version of the core are you trying. Please try with the 2016.4 version of the core and check if it works now.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Visitor yweehong
Visitor
3,032 Views
Registered: ‎09-19-2013

Re: Video Processing Subsystem 2.0 - Deinterlacer Only

I tried with the 2016.2 version.  Any idea when the Petalinux drivers will be out?

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