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Registered: ‎07-18-2011

Video Processing Subsystem - Deinterlacer not working at 1080i60

I am having difficulty getting the Video Processing Subsystem deinterlacer to function correctly at 1080i60 in an Artix-7.    The scaler, colorspace converter, and 4:2:2 to 4:4:4 chroma resampler all work fine, but the deinterlacer image is split vertically, displaying what looks like field 1 in the upper portion of the screen and field 2 in the lower portion of the screen, with some horizontal line noise throughout.


Deinterlacer image (1080i60 input, 1080p60 output):




Scaler image with progressive-scan input (it looks fine with either 720p60 or 1080p60 input, 1080p60 output, and other output resolutions):






Hardware setup:

 - Xilinx Artix-7 XC7A100T-2FGG484I  FPGA

 - Micron MT41K256M16TW-107 IT:P  4Gb (32Meg x 16 x 8 banks) DDR3 SDRAM running at 400MHz clock

 - MIG UI clock running at 100MHz

 - MicroBlaze clock running on MIG ui clock at 100MHz

 - Video in data stream coming from HD-SDI source running at 1080i60 (74.25MHz)

 - AXI4-Stream clock on all IP between video in and out running at 148.5MHz

 - Video Input to AXI4-Stream and AXI4-Stream outputs running at 148.5MHz single pixel, with AXI4-Stream data width

    converter IP to convert to 2 pixels per clock before and after the Video Processing subsystem

 - Scaler setup:

     - Full-fledged mode

     - 2 clocks per pixel

     - 8-bit data width

     - 2240 max pixels

     - 1280 max lines

     - built-in DMA enabled, connected to MIG

     - interlaced input enabled, deint field id coming from HD-SDI 1080i source field signal

     - RGB | YUV 4:4:4 | YUV 4:2:2

     - motion-adaptive deinteralcing enabled

     - Polyphase scaling (default settings)

     - FIR chroma resampler 4 taps

    - color matrix demo window off



I have tried using the example code from XAP1291 adapted to my board hardware, and also tried code from another example project, but I get the same results with both.



The frame buffer start is offset and the linker script generated to leave room to run code from DDR3, since it won't fit in block RAM:

  - :#define USR_FRAME_BUF_BASEADDR     (XPAR_MIG7SERIES_0_BASEADDR + (0x00080000))


Following is the input timing from the Video Timing controller API calls in 1080i60 input mode (timing detector is configured for

Hblank/Vblank/Active inputs only, no Hsync/Vsync)

     XVtc_GetDetectorTiming(PeriphPtr->Vtc1Ptr, &InputTiming);
     videoMode = XVtc_GetDetectorVideoMode(PeriphPtr->Vtc1Ptr);


active H = 1920
active V = 540
H front porch = 0
H sync = 0
H back porch = 280
V front porch = 0
V sync = 23
V back porch = 1
Interlaced = 1
Video mode = 100


This is the output from the XVprocSs_ReportSubcoreStatus(Vpss1Ptr, XVPROCSS_SUBCORE_VDMA); API call:


----->VDMA IP STATUS<----

INFO: VDMA Rd/Wr Client Width/Stride defined in Bytes Per Pixel
Bytes Per Pixel = 3.0
Read Channel Setting

Dump register for channel 44A00000:
    Control Reg: 1008B
    Status Reg: 10000
    CDESC Reg: 0
    TDESC Reg: 0
Height: 1080
Width : 5760 (1920)
Stride: 5760 (1920)

Write Channel Setting

Dump register for channel 44A00030:
    Control Reg: 10003
    Status Reg: 10000
    CDESC Reg: 0
    TDESC Reg: 0
Height: 1080
Width : 5760 (1920)
Stride: 5760 (1920)



This is the output of the  XVprocSs_ReportSubcoreStatus(Vpss1Ptr, XVPROCSS_SUBCORE_DEINT); API call:


----->Deinterlacer IP STATUS<----
IsDone:  1
IsIdle:  0
IsReady: 0
Ctrl:    0x81
Read Frame Buffer:  0x83304000
Write Frame Buffer: 0x83304000
Color Format:       2
Algo Selected:      0
Width        :      1920
Height       :      540



Following are my calculations for memory and bandwidth requirements, per UG934


Scaler Max width: 1920 pixels          
Scaler Max height: 1080 lines          
Deinterlacer max width: 1920 pixels          
Deinterlacer max height: 1080 lines          
Max components 3 components   RGB= 3, Y/CbCr = 2      
Byes per component 1 bytes   8-bit data = 1, 10/12/16 bit data = 2      
Frame rate 60 Hz          
Memory width: 16 bits          
DDR memory freq: 400 MHz          
Memory requirements              
Scaler: 30 Mbytes   Note: 5 frame buffers required      
Deinterlacer: 9 Mbytes   Note: 3 frame buffers required for deinterlacer      
Scaler+deinterlacer: 39 Mbytes          
Bandwidth requirements              
Scaler write: 356 Mbytes/sec   Note: writes 1 frame and reads 1 frame      
Scaler read: 356 Mbytes/sec          
Scaler total: 712 Mbytes/sec          
Deinterlacer write: 178 Mbytes/sec   Note writes 1 field and reads 2 fields      
Deinterlacer read: 356 Mbytes/sec          
Deinterlacer total: 534 Mbytes/sec          
Scaler+deinterlacer: 1246 Mbytes/sec          
Memory capacity: 1526 Mbytes/sec          



Is the theoretical max memory bandwidth capacity of 1526 Mbytes/sec just too close to the 1246Mbytes/sec required?   If it is I would think it would just have corrupted data, not a top/bottom split like shown in the image above, which looks like it is just writing both fields in sequence into memory, instead of generating a full 1080 line field from each 540 line input field.


In addition, I think the max height for the deinterlacer should be 540, not the 1080 I have shown in my table, which would drop the total bandwidth requirements for the scaler+deinterlacer to 979 Mbytes/sec, which I would think should be plenty of margin.


Also, I get the same sort of results with a 720p60 output, which should be even lower throughput bandwidth. 


As a test, for higher throughput, I tried increasing the data width to 4 pixels per clock (96-bit AXI4-Stream path) with the exact same results.


Any ideas?  


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4 Replies
Registered: ‎07-18-2011

Re: Video Processing Subsystem - Deinterlacer not working at 1080i60

A bit more info from the Video Processing subsystem config report, showing the dinterlacer is apparently in the path:



    Color Format:     YUV_422
    Color Depth:      8
    Pixels Per Clock: 4
    Mode:             Interlaced
    3D Format:        Frame Packing
    Frame Rate:       60Hz
    Resolution:       1920x1080@60Hz (I)
    Pixel Clock:      74250000

    Color Format:     RGB
    Color Depth:      8
    Pixels Per Clock: 4
    Mode:             Progressive
    Frame Rate:       60Hz
    Resolution:       1920x1080@60Hz
    Pixel Clock:      148500000

Zoom Mode: OFF
Pip  Mode: OFF
Data Flow Map: VidIn -> DEINT -> VDMA -> SCALER-V -> SCALER-H -> LBOX -> CR-H -> CSC -> VidOut


Also, the bandwidth calculation in my spreadsheet did take into account 540 lines instead of 1080 lines for the deinterlacer, so the higher 1246Mbytes/sec rate should be correct, not 979Mbytes/sec as i stated in the post above.


0 Kudos
Registered: ‎11-09-2015

Re: Video Processing Subsystem - Deinterlacer not working at 1080i60

Hi @reaiken,


You should start with the VPSS configured as Deinterlacer only.


There is a small programming sequence. The example is in the deinterlacer only example design. Make sure that the C instance of the deinterlacer is memset or assigned to an actual value.

Make sure to note the function XPeriph_resetHlsIP. It is a requirement to reset the Deinterlacer after an input change. The Deinterlacer only configuration does not do this automatically


If you cannot make it work with the deinterlacer example, please let me know and I will work with you to find the issue.





Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Registered: ‎07-18-2011

Re: Video Processing Subsystem - Deinterlacer not working at 1080i60

Thank you very much, it sounds like my problem is most likely incorrect SW setup for the deinterlacer.


Where do I find the deinterlacer only example design?   I don't see it in any of the documentation for the IP.



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Registered: ‎11-09-2015

Re: Video Processing Subsystem - Deinterlacer not working at 1080i60

Hi @reaiken,


The flow to generate the example design is mentioned in the PG231(link) chapter 5.


Basically, what you need to do is:

1. In vivado, add the IP to a project and configure it as deinterlacer only

2. Right click on the IP and generate the example design.

3. Generate the bitstream and export the Hardware (hdf file) to the VPSS driver location (SDK installation folder).

4. Then source the script to generate the SW example.


Hope that helps,





Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**