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4,472 Views
Registered: ‎07-19-2016

Video Processing Subsystem IP Scaler Only Outputs to Cero

Hi, i`m trying to evaluate the Video Processing subsystem Ip Core with a Zynq-7000 using the pico zed and a carrier card v2 from avnet, not successfully so far. Running out of ideas now. I took the Xilinx`s Example for the KC705 Board  which use  a microblaze proccessor and adapted it to the zynq like in the picture:

 

block diagramm

 

Before adding the VPSS i tested i simpler video chain and it works properly so i know they are configured ok, this are the otuput from the TPG, it seems like the VPSS can`t read the data which is valid. The TDATA is always 00FFFF

p.JPG

and this the output from the VPSS

p3.JPG

Obviously the Axis to Video Output never locks, here are the output from the Logger in the bare-metal application:

p4.JPG

I'm following the reference design steps:p5.JPG

By the way my license is evaluation hardware, this is not related is it? Any hints? Thanks in advance.

 

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6 Replies
Xilinx Employee
Xilinx Employee
4,447 Views
Registered: ‎07-31-2012

Re: Video Processing Subsystem IP Scaler Only Outputs to Cero

Hi, This should not be a hardware evaluation license issue. Which version of the Vivado are you using? Can you use the sw provided with the XAPP1291 and try running this- http://www.xilinx.com/support/documentation/application_notes/xapp1291-video-subsystem.pdf

Also what are the inputs and output color formats? Is this in full fledged mode or Scaler only mode?
Thanks,
Anirudh

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4,438 Views
Registered: ‎07-19-2016

Re: Video Processing Subsystem IP Scaler Only Outputs to Cero

hello, thanks for your answer,

 

i`m using vivado 2016.2 . I have this configuration:

------ SUBSYSTEM INPUT/OUTPUT CONFIG ------
->INPUT
Color Format: RGB
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 800x600@60Hz
Pixel Clock: 39790080

->OUTPUT
Color Format: RGB
Color Depth: 8
Pixels Per Clock: 1
Mode: Progressive
Frame Rate: 60Hz
Resolution: 800x600@60Hz
Pixel Clock: 39790080

 

The VPSS is in Scaler only mode,

 

i will check the xapp1291-video-subsystem .

 

So far for the software i was using the example from xilinx      \Xilinx\SDK\2016.2\data\embeddedsw\XilinxProcessorIPLib\drivers\vprocss_v2_0\examples\src

 

 

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Xilinx Employee
Xilinx Employee
4,429 Views
Registered: ‎08-02-2011

Re: Video Processing Subsystem IP Scaler Only Outputs to Cero

Hello,

 

xapp1285 shows scaler only mode with software running on the ARM in Zynq.

https://www.xilinx.com/support/documentation/application_notes/xapp1285-scaling-video-processing-with-vpss.pdf

www.xilinx.com
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4,403 Views
Registered: ‎07-19-2016

Re: Video Processing Subsystem IP Scaler Only Outputs to Cero

Hi, i have try to rebuild the hardware application but this was made in vivado 2015.4 and it does not work in newest versions. Do you have a scheme of the Block Diagramm a could follow? I tried with the src files inside this reference design and adapted them to my hardware with not sucess. How could i debug the AXIS ? I have connected ILAs in the design but from here not exactly what is happening or how to solved it.

 

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Observer borial
Observer
2,143 Views
Registered: ‎05-14-2013

Re: Video Processing Subsystem IP Scaler Only Outputs to Cero

the TREADY of VPSS' output to TPG never goes high, I encounter the same issue, have you solve it ?

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Moderator
Moderator
2,117 Views
Registered: ‎11-09-2015

Re: Video Processing Subsystem IP Scaler Only Outputs to Cero

HI @borial,

 

Please open a new thread for your issue.

 

And the VPSS requires to follow some steps. You might want to start with the example design fro vivado.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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