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Visitor
Visitor
6,008 Views
Registered: ‎06-08-2016

Video Processing Subsystem Master/Slave clock rate

Hello,

   As Video Processing Subsystem replaces scaler, deinterlacer, chroma resampler, etc, VPS is recommended for new designs. But there is one concept that vanished from Scaler (Old stand alone version) --> to VPS. Different master and slave clk in Axi-Stream ports.

With VPS, I want to perform a simple live up-scaling (from 1024x768p@50 to 1280x720p@50) and I want to keep the same frame rate. Why do Master & Slave interfaces in VPS share the clk? Obviously, the pixel rate would change as the resolution has increased.

My source of video (1024x768p@50) is 40MHz pixel-rate and I want to transmit the scaled video (1280x720p@50) through an HD SDI at 74.25MHz. How I am supposed to manage the different clk rates?

 

Thanks In Advance

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Xilinx Employee
Xilinx Employee
5,975 Views
Registered: ‎08-02-2011

Re: Video Processing Subsystem Master/Slave clock rate

Hello,

 

Good question. It's much simpler than the old scaler in an effort to solve some of the associated difficulties there.

 

You basically need to run the clock at the fastest pixel rate that you need to deal with. So for your use case, run it at 74.25MHz.

www.xilinx.com
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