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Contributor
Contributor
859 Views
Registered: ‎04-10-2018

Video Test Pattern Generator Vertical Blanking

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Hello All!

I'm trying to send a Test Pattern to a MIPI CSI2 Tx IP. The pattern is sent by a Video Test Pattern Generator IP (VTPG) via AXI-Stream. But as I can see, the pattern is continuously sent, that is, the vertical blanking (null pack between two frames) is the same of the horizontal blank (null pack between two lines).

The pattern is a 1920x1080 RAW10 at axis_clk = 100 MHz. I need to send the sequence of frames with a vertical blanking of 800 lines. Once the MIPI only sends the data when it is on its input, I need to configure the VTPG to generate this blanking.

How can I select the vertical blanking from VTPG? Is it a native configuration or I'll need another IP?

Thank you all for help.

Regards,

Marcos

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1 Solution

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Moderator
Moderator
909 Views
Registered: ‎11-09-2015

Re: Video Test Pattern Generator Vertical Blanking

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Hi @marcos.bissiano,

 

The test pattern generator is outputting in the AXI4-Stream format for Xilinx video IPs as per UG934 which does not carry the blanking or sync signals:

UG934.PNG

 

You will not be able to do this with the TPG.

 

The way to do native interface would be to add a AXI4-Stream to video out + a VTC after the TPG as per my Video Beginner Series 6: From AXI4-Stream to Native Video

 

Regards,

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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5 Replies
Xilinx Employee
Xilinx Employee
824 Views
Registered: ‎03-30-2016

Re: Video Test Pattern Generator Vertical Blanking

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Hello Marcos @marcos.bissiano

# I believe your MIPI CSI-2 TX is using Native Video Interface.


- In the other hand, Video Test Pattern Generator IP has only AXI4-stream output interface,

  This VTPG IP will not match your FPGA design, since it cannot generate blanking-period data.

- Xilinx also offer other test pattern generator IP, but this IP does not support Native video interface too.

     https://www.xilinx.com/products/intellectual-property/axi_tg.html
     https://www.xilinx.com/support/documentation/ip_documentation/axi_traffic_gen/v3_0/pg125-axi-traffic-gen.pdf

 

Hello @florentw, Hello @samk
Do we have Video test pattern generator IP that support native video interface ?

If YES, could you give some IP recommendation to Marcos ?

If there is no available IP, I think @marcos.bissiano need to create the new one. 

 

Best regards

Leo

 

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Moderator
Moderator
910 Views
Registered: ‎11-09-2015

Re: Video Test Pattern Generator Vertical Blanking

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Hi @marcos.bissiano,

 

The test pattern generator is outputting in the AXI4-Stream format for Xilinx video IPs as per UG934 which does not carry the blanking or sync signals:

UG934.PNG

 

You will not be able to do this with the TPG.

 

The way to do native interface would be to add a AXI4-Stream to video out + a VTC after the TPG as per my Video Beginner Series 6: From AXI4-Stream to Native Video

 

Regards,

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Contributor
Contributor
799 Views
Registered: ‎04-10-2018

Re: Video Test Pattern Generator Vertical Blanking

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Hello Florent @florentw and Leo @karnanl

@karnanl:
# I believe your MIPI CSI-2 TX is using Native Video Interface.
No, My CSI-2 Tx is configured to AXI-Stream. I'm using the VTPG to send frames, but it hasn't the V_Blank.

- In the other hand, Video Test Pattern Generator IP has only AXI4-stream output interface,
  This VTPG IP will not match your FPGA design, since it cannot generate blanking-period data.
Thank you for this information, is what I want to know.

- Xilinx also offer other test pattern generator IP, but this IP does not support Native video interface too.
I think this IP may help me to resolve my problem. I'll study the IP and think about it.

@florentw:
Thank you too for this information, it was exactly what I thought.

I'll make the tutorial and see what can I do.

Once I'm sendding MIPI data from my FPGA using the VTPG (I also capture a frame), the VTPG is configured, and I'm sending it totally via AXI-Streaming, what is the best way to follow in your opinion? Start to use the new IP, trying to configure it or use the VTC after the VTPG, or using the VTC and changing the input of my CSI-2 Tx to native video?

Thank you all

Regards.

Marcos,

Moderator
Moderator
751 Views
Registered: ‎10-04-2017

Re: Video Test Pattern Generator Vertical Blanking

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Hi @marcos.bissiano,

 

No, My CSI-2 Tx is configured to AXI-Stream. I'm using the VTPG to send frames, but it hasn't the V_Blank. 

....

Once I'm sendding MIPI data from my FPGA using the VTPG (I also capture a frame), the VTPG is configured, and I'm sending it totally via AXI-Streaming, what is the best way to follow in your opinion? Start to use the new IP, trying to configure it or use the VTC after the VTPG, or using the VTC and changing the input of my CSI-2 Tx to native video?

 

If you are using the AXI-Streaming interface, you do not need the VTC because there is no VBLank signal. Please see PG260, page 43.

 

***EDIT*** Correct screenshot -Sam

2018-08-10 11_11_21-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

 

 

Regards,

Sam

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
Contributor
Contributor
699 Views
Registered: ‎04-10-2018

Re: Video Test Pattern Generator Vertical Blanking

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Hello Guys!

 

I change my TPG/CSI interface to communicate via Native Video using a VTC and it works perfectly. With this result, me and my team advanced a lot in our project.

 

Thank you all for the Help and best regards!