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Explorer
Explorer
634 Views
Registered: ‎09-13-2011

Video Test Pattern Generator can't simulate

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Untitled.jpg

I'm just trying to simulate an instance of the Video Test Pattern Generator however it is not responding. It is like it isn't there but it is! I'm using 2018.3.

 

 

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Moderator
Moderator
496 Views
Registered: ‎11-09-2015

Re: Video Test Pattern Generator can't simulate

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Hi @tsjorgensen,

I do not see ARVALID or AWVALID asserted by your BFM so it might be your issue. If the address is not correctly set, do not expect the read or write to happen.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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10 Replies
Scholar watari
Scholar
584 Views
Registered: ‎06-16-2013

Re: Video Test Pattern Generator can't simulate

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Hi @tsjorgensen

 

Do you assert enough cycles of reset signal ?

Xilinx's FIFO which is used by a lot of Xilinx's IP requests at least 5 cycle of slower clock.

 

Best regards,

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Explorer
Explorer
570 Views
Registered: ‎09-13-2011

Re: Video Test Pattern Generator can't simulate

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I had the same thought so made sure it gets more than 32 cycles of the slow Video clock of reset. Seems like simulation model just doesn't work. In hardware I can access the core but not in simulation.
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Scholar watari
Scholar
553 Views
Registered: ‎06-16-2013

Re: Video Test Pattern Generator can't simulate

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Hi @tsjorgensen

 

I see.

Do you use Zynq or Zynq MPSoC ?

If yes, you need to use Zynq VIP (Verification IP) to simulate a design.

If no, would you share like your block diagram ?

 

Best regards,

 

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Explorer
Explorer
536 Views
Registered: ‎09-13-2011

Re: Video Test Pattern Generator can't simulate

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Device is Zynq 7030.

It's not BD but instance in a VHDL testbench, signals shown are taken from inside the instance.

We have our own scripted AXI BFM master that has worked for years with multiple cores, but could be that this core requires something special. Just doesn't seem to point that way with the X's out from the core. Wondering if there's still a license issue as this core has only just stopped requiring a license.

Story is that we made a video design for a small color LCD of 320x240 pixels, first we tried the VDMA but couldn't get a lock from the Stream-to-Video-Out, then we tried the VTPG but still can't get lock. In hardware we can write to all the cores and they seem to respond meaningful. We are pretty sure we set up for the correct amount of data, the correct number of pixels. Status vector on the Stream-to-Video-Out however says not-idle, no underrun, no overrun and both fine tune and coarse tune.

So I thought it would be a great idea to make a simulation of the cores. I could simulate the Video Timing Controller but not the VTPG using same environment.

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Moderator
Moderator
527 Views
Registered: ‎11-09-2015

Re: Video Test Pattern Generator can't simulate

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HI @tsjorgensen,

What configuration are you doing through the registers to configure the TPG? Note that you need to start the TPG at address 0x0 before getting any output.

You might want ot use my Video Series 4 as reference to get started.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
514 Views
Registered: ‎09-13-2011

Re: Video Test Pattern Generator can't simulate

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In hardware we tried the following:

poke 0x60010010 0x00000140
poke 0x60010018 0x000000f0
poke 0x60010020 0x00000009
poke 0x60010040 0x00000000
poke 0x60010000 0x00000081

Where 0x60010000 is base address for the VTPG.

Followed by:

poke 0x60000000 0xc1ffff07
poke 0x60000060 0x014000f0
poke 0x60000070 0x00000140
poke 0x60000074 0x01450145
poke 0x60000078 0x013E013D
poke 0x60000080 0x01430142
poke 0x60000068 0x00000002
poke 0x6000006C 0x0000007f
poke 0x6000007c 0x00f000f0
poke 0x60000084 0x00f000f0
poke 0x60000088 0x00f000f0
poke 0x60000090 0x00f000f0
poke 0x60000000 0x01ffff07

Where 0x60000000 is base address for the VTC.

But this is in hardware and peeking works there too.

In our simulation it gets stuck on the very first write that is never acknowledged, ready signal doesn't go high.

Regards,

tsjorgensen

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Moderator
Moderator
509 Views
Registered: ‎11-09-2015

Re: Video Test Pattern Generator can't simulate

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Hi @tsjorgensen,

Could you show the AXI-Lite interface with more detail.

I am intersted on when you first set the read address (i.e. the first transaction)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
503 Views
Registered: ‎09-13-2011

Re: Video Test Pattern Generator can't simulate

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The picture is the first transaction (write in local address 0x10).

Maybe there is a better format I can post the full simulation? But it is really just release of reset before that.

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Moderator
Moderator
497 Views
Registered: ‎11-09-2015

Re: Video Test Pattern Generator can't simulate

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Hi @tsjorgensen,

I do not see ARVALID or AWVALID asserted by your BFM so it might be your issue. If the address is not correctly set, do not expect the read or write to happen.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
483 Views
Registered: ‎09-13-2011

Re: Video Test Pattern Generator can't simulate

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So true!

It turns out our BFM can't handle that awready is asserted before awvalid. Fixed it and now I can read and write to the core.

Thank you @florentw

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