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Contributor
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Registered: ‎04-01-2008

Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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I am using Vivado 2017.3 on a windows 10 machine, and I have a block diagram that is basically the HDMI 2.0 TX Example design.  When I got to generating the OOC files, I get an error with Vivado generating the TPG block files, saying it can't find the files and can't synthesize.  This is the standard Xilinx IP.  

 

I moved the folder structure, so the path name shouldn't be too long.  Anyone else run into this, or have a solution?  I never saw this in 2017.2 for similar designs. 

 

Thanks.  Below is the output from the OOC generation:


-----------------------------------------------------------
# Vivado v2017.3 (64-bit)
# SW Build 2018833 on Wed Oct  4 19:58:22 MDT 2017
# IP Build 2016188 on Wed Oct  4 21:52:56 MDT 2017
# Start of session at: Fri Jan 26 07:51:36 2018
# Process ID: 17588
# Current directory: D:/FPGA_Projects/REV_2a/vivado/UHD_FPGA_TOP.runs/hdmi_ex_v_tpg_0_0_synth_1
# Command line: vivado.exe -log hdmi_ex_v_tpg_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source hdmi_ex_v_tpg_0_0.tcl
# Log file: D:/FPGA_Projects/REV_2a/vivado/UHD_FPGA_TOP.runs/hdmi_ex_v_tpg_0_0_synth_1/hdmi_ex_v_tpg_0_0.vds
# Journal file: D:/FPGA_Projects/REV_2a/vivado/UHD_FPGA_TOP.runs/hdmi_ex_v_tpg_0_0_synth_1\vivado.jou
#-----------------------------------------------------------
INFO: [Common 17-1460] Use of init.tcl in D:/Xilinx/Vivado/2017.3/scripts/init.tcl is deprecated. Please use Vivado_init.tcl
Sourcing tcl script 'D:/Xilinx/Vivado/2017.3/scripts/init.tcl'
281 Beta devices matching pattern found, 0 enabled.
source hdmi_ex_v_tpg_0_0.tcl -notrace
Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 439.848 ; gain = 72.934
INFO: [Synth 8-638] synthesizing module 'hdmi_ex_v_tpg_0_0' [d:/FPGA_Projects/REV_2a/src/HDMI_SS/ip/hdmi_ex_v_tpg_0_0/synth/hdmi_ex_v_tpg_0_0.v:57]
ERROR: [Synth 8-439] module 'hdmi_ex_v_tpg_0_0_v_tpg' not found [d:/FPGA_Projects/REV_2a/src/HDMI_SS/ip/hdmi_ex_v_tpg_0_0/synth/hdmi_ex_v_tpg_0_0.v:156]
ERROR: [Synth 8-285] failed synthesizing module 'hdmi_ex_v_tpg_0_0' [d:/FPGA_Projects/REV_2a/src/HDMI_SS/ip/hdmi_ex_v_tpg_0_0/synth/hdmi_ex_v_tpg_0_0.v:57]
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 481.602 ; gain = 114.688
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

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Moderator
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Registered: ‎11-09-2015

Re: Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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HI @jechambe-koe,

 

So it seems to be indeed linked to the HLS issue. We are working on a fix.

 

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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Hi @jechambe-koe,

 

There is a known issue with the HLS compiler on windows in 2017.3 and 2017.4 which is affecting the TPG and the VPSS IPs.

 

The workarounds I have found are:

  • Use linux to generate the design
  • For the HDMI example design it should work if the HDMI IP is configured in 2ppc but not in 4 ppc

 

The resolution of this issue is on-going.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎04-01-2008

Re: Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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Hi florentw,

 

Thanks for getting back to me.  I was just installing 2017.4 to see if that would fix the issue, but I guess it won't.  I don't have a Linux environment that I can use, so I think I am going to have to re-produce the Block diagram in 2017.2.   (unless there was some magical way to import a 2017.3 block diagram into 2017.2 to save me an hour or so??) 

 

Also, I am using the IP in 2 pixel per clock, but I still get this error. 

 

Thanks.

Jechambe

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Registered: ‎11-09-2015

Re: Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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Hi @jechambe-koe,

 

Unfortunately I don't have any magic solution...

 

Could you just make sure this is the issue I am talking about by just checking the tpg license status (could you share a screenshot of vivado license manager) and reset the BD output products and regenerate the products.

 

Licensing issue for the TPG are sometimes hard to catch. You should have a vivado_hls log created into the directory for the TPG, could you share it?

 

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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Sure, here is my License manager screen shot:

 

License

 

I have reset the TPG outputs, and then I clear the cache as well using the "config_ip_cache - clear_local_cache" command.  All with no luck. 

 

So the weird thing is, I created the HDMI 2.0 TX only Example design just fine with 2017.3, as that is the 1st time that a TX Only reference design was offered.  I regenerated it a bunch of times, added in a 2nd HDMI 2.0 TX interface (copy of the 1st channel) and rebuilt it about 2 dozen times without any issues.  All of a sudden I am having these issues. 

 

Capture2.JPG

 

 

Thanks.

jechambe

 

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Moderator
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Registered: ‎11-09-2015

Re: Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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HI @jechambe-koe,

 

So it seems to be indeed linked to the HLS issue. We are working on a fix.

 

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎04-01-2008

Re: Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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Since I have your attention, :), I am attempting to recreate the HDMI TX only block diagram in 2017.2, but one of the components of the TX Only reference design, the "Video Frame CRC" component isn't any where in the IP catalog.  What is this for, and is it needed for proper operation? 


I can't seem to find any documentation on it, or what it does.   If it is needed, how can I add it to the IP catalog of 2017.2? 

 

Thanks again for the help.


Jechambe

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Re: Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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Hi @jechambe-koe,

 

The video CRC is part of what we call the helper cores.

 

They are used in the reference designs to give some information and help checking the good behavior of the HDMI IP in the design.

They are not needed to use the HDMI (or other IP from the catalog) and are just here for reference.

 

They are not supported by Xilinx (they are created by Xilinx but just for "reference"), this is why they are not in the IP catalog and if you need to have one of this block, you should create your own IP.

 

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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Hi florentw,

 

As an experiment I created the HDMI 2.0 TX block diagram in 2017.4 (exact same thing I was doing in 2017.3 that failed), and the TPG now successfully synthesizes.  My block diagram now seems to be OK in 2017.4, but not 2017.3.  So, could it be a different problem than the above mentioned HLS issue?

 

Thanks


jechambe

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Re: Video Test Pattern Generator v 7.0, VIvado 2017.3 can't find files to synthesize ..

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HI @jechambe-koe,

 

Yes... It could be a different problem but I have never experienced it...

 

Could you share the hls log failing for the TPG?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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