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Visitor
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Registered: ‎02-27-2015

Video Timing Controller v6.1: Problem with interlaced video generation

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I try to generate a 480i video output with the Xilinx Video Timing Controller.

 

There seem to be some problems with that core:
1. The signal field_id_out doesn't toggle.
2. The output doesn't seem to be interlaced. Also for the second field HSYNC and VSYNC have a synchronous rising edge and the VBLANK lengths is equal for every field.

 

Like described in AR#61228 (http://www.xilinx.com/support/answers/61228.html) I added an AXI-Lite interface and set the CONTROL register to enable the generation.  But it doesn't help, the field_id_out signal is still LOW the entire time.

 

Am I missing something? Do I have to set another register via AXI-Lite interface? (I don't need the AXI-Lite interface, for me it would be okay if it would work in constant mode)


Thanks for any help.
Lars

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: Video Timing Controller v6.1: Problem with interlaced video generation

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Hi Lars,

Did you set the 'Interlaced' bit in the generator encoding register?

You should also make sure to write the 'Reg Update' and 'sw_enable' bits in the control register after writing the generator encoding register.
www.xilinx.com

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: Video Timing Controller v6.1: Problem with interlaced video generation

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Hi Lars,

Did you set the 'Interlaced' bit in the generator encoding register?

You should also make sure to write the 'Reg Update' and 'sw_enable' bits in the control register after writing the generator encoding register.
www.xilinx.com

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Visitor
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Registered: ‎02-27-2015

Re: Video Timing Controller v6.1: Problem with interlaced video generation

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Hi bwiec,

setting the Interlaced bit in the generator encoding register indeed works. Now field_id_out signal toggles and AXI-To-VideoOut Core locks. Thank you very much for your help!!

 

Xilinx should change the description in Table 2-7 of Video Timing Controller User Guide pg016. According to this table default value of register 0x0068 is specified via GUI, which doesn't seem to be correct.

 

Best regards, Lars

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: Video Timing Controller v6.1: Problem with interlaced video generation

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Hey Lars,

 

Oh okay, great! Yeah, we'll be fixing it. Sorry for the inconvenience.

 

Best,

Brian

www.xilinx.com
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Anonymous
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Re: Video Timing Controller v6.1: Problem with interlaced video generation

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Hi @bwiec @larsb

 

Could you be little more explicit and tell me how this issue was solved? I use Vivado 2015.2. I have posted my question here. I am facing a very similar problem.

 

Regards,

 

Meghana.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: Video Timing Controller v6.1: Problem with interlaced video generation

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Hi Meghan,

 

What exactly is unclear still?

 

From page 38 here:

http://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_1/pg016_v_tc.pdf

 

shows the mapping for the Generator Encoding register (offset 0x68). Bit 6 of that register is the 'Interlaced' bit which defaults to 0. You need to write it to 1, telling the core to generate interlaced content.

www.xilinx.com
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Anonymous
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Re: Video Timing Controller v6.1: Problem with interlaced video generation

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@larsb@bwiec

Is this problem of interlacing fixed in the higher versions of VTC? I am using v6.1 currently.

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Anonymous
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Re: Video Timing Controller v6.1: Problem with interlaced video generation

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Thanks. @bwiec @larsb

 

I am now calling the functions on SDK:

XVtc_ConvVideoMode2Timing();
XVtc_SetGeneratorVideoMode();

The output on monitor is as shown here.

 

 

I noticed that VTC is generating twice the required frequency of sync signals. (HSYNC: 31.25KHz  and VSYNC: 100Hz is generated. Ideally, PAL should have HSYNC: 15.625KHz  and VSYNC: 50Hz)

 

What do you suspect is the issue here?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: Video Timing Controller v6.1: Problem with interlaced video generation

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Hello,

Hmm maybe clocking? What clock (how fast) is driving the VTC clock?

I'd also probe it with an ILA and see if the number of pixels between hsyncs is correct.
www.xilinx.com
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