Video Timing Controller v6.1 detection problem

[wtneo@leica]

Hi,

  I am having problem getting vtc to detect video timing from Video to AXIS IP.  My timing controller "my_tc" is unable to lock even though Active video, HBLANK and VBLANK are present.  Its intc_if port reads 0x00002a7e.  Decoding this bit pattern suggest that is not LOCKED and VBLANK is not detected.

  So I created a reference vtc called "working_tc", set to 1080P mode, to generate known good video timing signals and check its output with "working_tc_checker".  "working_tc_checker" is able to lock, ie intc_if[8] output is '1'.  intc_if[31:0] port reads 0x0000097F. 

  Then I compare my Video in to AXI4-Stream output against "working_tc" output.  They are exactly the same, but shifted in phase.  Both HBLANK is 280 clk long. Both horizontal are 2200 clocks.  Active Video is exact inversion of HBLANK.  Both VBLANK is 45 HBLANK periods.  Both Vertical are 1125 HBLANK periods.

  Also,  rising edge of HBLANK coincides with rising edge of VBLANK on my tc, same as "working_tc".

  Above ILA capture, "working" signals are produced by reference tc and is able to be locked by "working_tc_checker".   "AXIS" signals are output from Video In to AXI4-Stream IP, are not lockable.

Pls advice.

[watari]

Hi wtneo@leica

It seems VBLANK issue.

If you already prepared VSYNC and HSYNC, I suggest using VSYNC, HSYNC and ACTIVE_VIDEO to resolve this issue.

Would you try it ?

Best regards,

[wtneo@leica]

Hi Watari,

  I was using BLANKs instead of SYNCs because the output from Unsupported SDI to Video bridge has only BLANKs.  Also, SDI transmission natively uses BLANKs so it straight forward to translate SDI control signals to BLANKs.  And I don't have to worry about front and back porches.

Regards,

Neo

[watari]

Hi wtneo@leica

Is there HBLANK signal as active during VBLANK is active ?

Would you make sure ?

BTW, can you implement firmware in your design ?

If yes, I suggest using "Video Timing Controller" IP to detect video timing and to generate video timing.

Best regards,

[wtneo@leica]

Hi Watari,

  Yes HBLANK is active during VBLANK.

  What do you mean by implementing firmware?  Do you mean connecting VTC checker to Microblaze via AXI, then read the registers to understand for errors?

Regards,

Neo

[watari]

Hi wtneo@leica

Yes. You connect VTC and implement control software with bare metal  driver at Microblaze.

Would you refer the following URL at page 22 ?

https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf

Best regards,

[wtneo@leica]

Hi Watari,

  But that document does not directly address detection problem.  Does the software API has function call to help debug detect error?

Regards,

Neo

[florentw]

Hi Neo,

Could you provide the exact video timing for the non-working case? It would be interesting to feed the exact same with the VTC as generator.

You are mentioning that you do not care about front and back porch. Could you still try to add one clock for each? I am not sure if any standard timing as a fp or bp of 0.

Best Regards,

[wtneo@leica]

Hi Florentw,

  I am unable to capture the entire video frame timing for the non-working case in one single capture because there is insufficient memory in ILA.  Do you have any suggestions how I can present video timings here?

  If I enable AXI interface on Video Timing detector, will I be able to read the detector registers and use it to debug why it cannot lock?  Will the detector registers contain any useful info when it is not locked in the 1st place?

  I do not understand your suggestion on fp and bp.  Output from Video in to AXI-Stream has only VBLANK and HBLANK,  how do I add 1 clk for fp and bp?

Regards,

Neo

[watari]

Hi wtneo@leica

Can you try them ?

1) Implement vertical counter whose trigger is the rising edge of horizontal blanking for debugging.

2) Use oscilloscope to measure signals of horizontal blanking and vertical blanking on FPGA port.

3) Capture waveform by the following triggers for insufficient memory

- Rising edge of horizontal blank and vertical blank.

Would you try them, if possible ?

Best regards,

[wtneo@leica]

Hi,

  I implemented the counters, sample below

always @ (posedge rx0_usrclk) begin
		axis_hblank_q			<=	axis_hblank_i;
end

always @ (posedge rx0_usrclk)
	if (axis_vblank_q == 1'b0 && axis_vblank_i == 1'b1)
		cnt_axis_vblank_h <= 1;
	else if (axis_vblank_i == 1)
		cnt_axis_vblank_h <= cnt_axis_vblank_h + 1;

Below is the counter values for input to my VTC.The stable value are the length of respective BLANK signals, eg VBLANK high = 99000 pclkHere is same capture zoomed into VBLANK startingHere is same capture with HBLANK endingVBLANK with HBLANK (HBLANK too dense, blur). VBLANK period 33.33msZoom into VBLANK high, contains 45 HBLANK periodsZoom into VBLANK and HBLANK rising. HBLANK period 29.6usZoom into HBLANK rising. Synchronous with VBLANK rising. HBLANK high for 3.79usHBLANK rising with PCLK = 72.6MHz

Thanks for the attention.

Regards,

Neo

[wtneo@leica]

Hi Watari,

  I would also like to show you the ILA capture of a working VTC timing output.

Counter values are the same. The working VTC port intc_if outputs 0x0000097f whereas my non-working VTC port intc_if outputs 0x00002a7e. My bit[8] =0 meaning not locked.

[watari]

Hi wtneo@leica

It seems wrong vertical setting or signal.

Is the video timing "1920 (Horizontal) x 280 (Vertical)" ?

If no, I suggest checking video timing on IO port via VIO and sharing it.

Also, could you explain the meaning of yellow and green on the waveform of osciloscope.

Best regards,

[wtneo@leica]

Hi Watari,

  280 is the length of HBLANK pulse in number of pclk.  VBLANK, HBLANK and Active_video are measured in number of pclk.

So the waveform reads:

  HBLANK pulse length = 280 pclks

  HBLANK period           = 280 + 1920                     =  2200 pclks

  VBLANK pulse length = 99000  pclks                    = 99000 / 2200 = 45 line periods

  VBLANK period           = 99000 + 2376000 pclks  = 2475000 / 2200 = 1125 line periods

The numbers matched a video timing generator I created to compare.  But mine timing detector failed to lock whereas another detector connected to the timing generator can lock.

Regards.

Neo

[florentw]

Hi wtneo@leica,

Can you check if you have front porch and back porch in your failing case (time between the end/beginning of active video and the beginning/end of the blanking pulse). In most video standards you are expected to have at least 1 pclk

Regards,

[wtneo@leica]

Hi Florentw,

  I am not aware of that.

  My video timing does not has any front porch and back porch.  ACTIVE_VIDEO goes high exactly when HBLANK goes low, and vice versa. 

  I modded the HBLANK signal to try your idea.

  HBLANK rising is delayed by 1 clock after ACTIVE_VIDEO falling.

  HBLANK falling is brought forward by 1 clock before ACTIVE_VIDEO rising (not shown).

  VBLANK rising and falling follows previous timing, ie. un-modded HBANK timing .

  The changes did not work, timing detector intc_if output reads 0x00002a7c.

  Anyway, the working VTC generator uses the same HBLANK and ACTIVE_VIDEO before my changes and it works.

Regards,

Neo

[florentw]

Hi wtneo@leica,

I think we should take one step back and look at a standard (CVT, VESA...) timing and see where your number differs.

Could you give:

* active HSIZE

* active VSIZE

* pixel clock

* VBLANK

* HBLANK

*Front porch

* Back porch

From my understanding, you are not sending the HSYNC and VSYNC to the VTC. Correct?

Regards,

[wtneo@leica]

Hi Florentw

  Yes I am not sending HSYNC and VSYNC to VTC.

* active HSIZE = 1920

* active VSIZE = 1080

* pixel clock = 148.5MHz

* VBLANK = 45 lines

* HBLANK = 280 pclk

*Front porch ? how to measure front porch when not using HSYNC?

* Back porch ? how to measure back porch when not using HSYNC?

Regards,

Neo

[watari]

Hi wtneo@leica

As you mentioned previous post (this reply), you set fv as 60Hz.

However as you uploaded the following picture, it shows as fv as 30Hz.

It's an inconsistency.

Would you make sure it ?

I'm sure that, at least it is a part of route cause.

Best regards,

[wtneo@leica]

Hi Watari,

  Thanks for tip.

  The clock source is from SDI IP core, seems like the IP is sending out 1080p30 and  74MHz clock.  

  I thought that Video Timing detection algorithm is not sensitive to pixel clock frequency.  I thought it merely measures the video timing signals input to it according to the clock provided to it.  In the GUI to configure IP core, I did not have to specify pixel clock frequency.

  Please correct me if I am wrong.

Regards,

Neo

[watari]

Hi wtneo@leica

Does your design have a frame buffer ?

If no, it's the route cause.

Because of you want to change vertical frequency from 30Hz to 60Hz.

If you don't want to change vertical frequency, I suggest using 72.25[MHz] as pixel clock.

Best regards,

[florentw]

Hi wtneo@leica,

Do you have any updates on this?

I do not think the VTC is sensible to the frame rate. So the issue might be in some number for the timing