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Explorer
Explorer
383 Views
Registered: ‎05-30-2017

Video on screen display OSD IP with interlace

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Hello I'm working with Vivado 2018.2 and Aritx-7 xc200t. To insert OSD i have two possible IP Video on-screen display that is deprecated but is free and Video Mixer that need a licence. In both I don't see native support for interlace. So using Video direct memory access I have to read a deinterlaced frame from DDR3 (previously written in DDR3 using CDMA and custom logic), elaborate deinterlaced frame with OSD IP and than write frame with OSD in DDR3 using Video Direct Memory Access. Is there an OSD IP that natively support interlace? Thank you.

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Moderator
Moderator
397 Views
Registered: ‎11-09-2015

Re: Video on screen display OSD IP with interlace

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Hi @pierlum,

 

First I need to still to recommend you to use the VPSS for any new solution. You might want to discuss that with your Xilinx contact

 

No the OSD does not support interlaced input. But the VPSS does ;)

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
1 Reply
Moderator
Moderator
398 Views
Registered: ‎11-09-2015

Re: Video on screen display OSD IP with interlace

Jump to solution

Hi @pierlum,

 

First I need to still to recommend you to use the VPSS for any new solution. You might want to discuss that with your Xilinx contact

 

No the OSD does not support interlaced input. But the VPSS does ;)

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**