UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
313 Views
Registered: ‎09-14-2009

Vivado 2018.1 SMPTE SDI IP synthesis

Jump to solution

Hi

I generated an SMPTE SDI core using Vivado 2018.1.  I found in the synth directory the IP core is just a wrapper around the component v_smpte_sdi_v3_0_8.  So rather than using the wrapper I instanciated the v_smpte_sdi_v3_0_8 component to reduce the files I had to manage in the design.  Similar to the way you can generate a clock gen using the IP manager and then just strip out the code you want like the MMCM and the BUFGs and not deal with the XCI during the build.  The UNISIM library contains all the MMCM and BUFGs so this isnt a problem.  When i do this for the v_smpte_sdi_v3_0_8 core, Vivado can't find the core anywhere.  I can sim the design just fine because i have the v_smpte_sdi_v3_0_8 sim library compiled. 

Is this a core that you have to use the wrapper and the XCI for it to build properly?  Is there a specific library I dont have causing it to show up as a black box?  I am using a non project mode approach.

Thanks

Joe Brackett

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
220 Views
Registered: ‎11-09-2015

Re: Vivado 2018.1 SMPTE SDI IP synthesis

Jump to solution

Hi @jcbrackett123,

The main difference between MMCM/BUFG and the SDI IP is that the MMCM/BUFG are element of the FPGA. Thus you can just call them directly as it is the same as would be the synthesis output.

While the SDI IP is HDL code. When you add the IP, this will generate all the VHDL/Verilog code. This is what is called by the wrapper. Thus I am quite sure you need to use the xci file (or you would need to add all the generated code files individually and you would not simplify your project structure).

Hope this is clear,

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
2 Replies
Highlighted
Moderator
Moderator
221 Views
Registered: ‎11-09-2015

Re: Vivado 2018.1 SMPTE SDI IP synthesis

Jump to solution

Hi @jcbrackett123,

The main difference between MMCM/BUFG and the SDI IP is that the MMCM/BUFG are element of the FPGA. Thus you can just call them directly as it is the same as would be the synthesis output.

While the SDI IP is HDL code. When you add the IP, this will generate all the VHDL/Verilog code. This is what is called by the wrapper. Thus I am quite sure you need to use the xci file (or you would need to add all the generated code files individually and you would not simplify your project structure).

Hope this is clear,

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
212 Views
Registered: ‎09-14-2009

Re: Vivado 2018.1 SMPTE SDI IP synthesis

Jump to solution

Hi

Thanks for your reply, this makes sense. 

Joe

0 Kudos