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Visitor yyamazaki
Visitor
187 Views
Registered: ‎06-20-2018

XA7Z030 4K60P

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XA7Z030 have only -1 speed grade.So -1 speed grade supports up to 2.7 Gb/s in DisplayPort RX Subsystem v2.1 supports, doesn't XA7Z030 recieve 4K60P of YCbCr422 10bit?

And  the package of XA7Z030 have FBG484 / FBV484.I want to use the DDR3 memory for the FrameBuffer,I use it in the HR bank.So the bandwidth of 32bit clock 400MHz is  25.6Gb/s,but the bandwidth of 4K60p R/W  needs about 32Gb/s.Is there any solution of this problem?

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Moderator
Moderator
113 Views
Registered: ‎11-09-2015

Re: XA7Z030 4K60P

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Hi @yyamazaki

You can use a MIG controller to implement the PL DDR.

The design can have both PS and PL DDR. Some of the Xilinx evaluation board (refer to the ZC706) have both PS and PL DDR. You can use it as reference

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
3 Replies
Moderator
Moderator
145 Views
Registered: ‎11-09-2015

Re: XA7Z030 4K60P

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Hi @yyamazaki 


@yyamazaki wrote:

XA7Z030 have only -1 speed grade.So -1 speed grade supports up to 2.7 Gb/s in DisplayPort RX Subsystem v2.1 supports, doesn't XA7Z030 recieve 4K60P of YCbCr422 10bit?

[Florent] - No there is no limitation. The limitation is only if you need HDCP (you will be able to support 2.7Gbps). But it might be difficult to meet timing on a -1 speedgrade with 4K.

The limitation is only if you need HDCP. In this case you can only reach 2.7Gbps

And  the package of XA7Z030 have FBG484 / FBV484.I want to use the DDR3 memory for the FrameBuffer,I use it in the HR bank.So the bandwidth of 32bit clock 400MHz is  25.6Gb/s,but the bandwidth of 4K60p R/W  needs about 32Gb/s.Is there any solution of this problem?

[Florent] - Using a PL DDR?


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor yyamazaki
Visitor
127 Views
Registered: ‎06-20-2018

Re: XA7Z030 4K60P

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Thank you for your answer,Florent.

 

[Florent] - Using a PL DDR?

Yes,I want to use a PL DDR.

The bandwidth of a PS DDR is about 34Gbps(32bit x 1066), but other resource(ARM,other AXI) use a PS DDR.So 4K60P Displayport is not enough bandwidth with a PS DDR.

Please tell me how to solve.

 

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Moderator
Moderator
114 Views
Registered: ‎11-09-2015

Re: XA7Z030 4K60P

Jump to solution

Hi @yyamazaki

You can use a MIG controller to implement the PL DDR.

The design can have both PS and PL DDR. Some of the Xilinx evaluation board (refer to the ZC706) have both PS and PL DDR. You can use it as reference

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**