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Newbie borinsky
Newbie
2,124 Views
Registered: ‎02-15-2018

XAPP1097 SDI interface - where are the VHDL wrappers?

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I'm trying to implement an SDI interface on Artix 7. I've downlaoded XAPP1097 and the associated ZIP containing the wrappers etc. It's got a set of Verilog files but where are the VHDL files? The app note ssays there are both VHDL and Verilog versions. I work in VHDL and my knowledge of Verilog is extremely limited so I'd rather not get involved with mixed languages.

 

This thread covers similar ground but doesn't answer my question:

https://forums.xilinx.com/t5/DSP-and-Video/SMPTE-SD-HD-3G-SDI-instance-missing-h-vhd-files-for-XAPP1097-GTP/m-p/787078/highlight/true#M17579

 

I'd appreciate your help and advice.

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Scholar drjohnsmith
Scholar
2,725 Views
Registered: ‎07-09-2009

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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I have no probelm with the core being what ever language Xilxin want.

 

But till recently, Xilinx supported both verilog and VHDL , and provided verilog wrappers for vhdl and verilog wrappers for vhdl.

 

Now if its a verilog core, no more a vhdl wrapper, 

  

Come on now.

 

If a wrapper is easy, then you can knock it out quickly and support it,

 

If a wrapper is hard, then not providing one , puts the none supported language at a significant disadvantage.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Moderator
Moderator
2,108 Views
Registered: ‎11-09-2015

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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Hi @borinsky,

 

From the xapp1097:

xapp.PNG

 

I don't know where you found that there was VHDL wrappers but this is not the case

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Newbie borinsky
Newbie
2,101 Views
Registered: ‎02-15-2018

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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Florent, on the first page of XAPP1097 v1.0.1 November 10, 2015, in the introduction:

 

The Xilinx SMPTE SD/HD/3G-SDI LogiCORE IP (hereinafter called the SDI core) can be
connected to an Artix-7 FPGA GTP transceiver to implement an SDI interface capable of
supporting the SMPTE SD-SDI, HD-SDI, and 3G-SDI standards. The SDI core and GTP
transceiver must be supplemented with some additional logic to connect them together to
implement a fully functional SDI interface. This application note describes this additional control
and interface logic and provides the necessary control and interface modules in both Verilog
and VHDL source code.

 

My bold.

 

If VHDL source really isn't available from Xilinx I'll try these translation tools: http://www.syncad.com/syn_v2v_down.htm

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Moderator
Moderator
2,097 Views
Registered: ‎11-09-2015

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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Hi @borinsky,

 

Ok I see. This is an error in the introduction. It is only available in verilog

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar drjohnsmith
Scholar
2,079 Views
Registered: ‎07-09-2009

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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Pity Xilinx are dropping support for VHDL,

 

Europe will miss you guys,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Moderator
Moderator
2,068 Views
Registered: ‎11-09-2015

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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Hi @drjohnsmith,

 

In this case it is not that Xilinx is dropping support for VHDL.

An xapp as mainly one author and he will have on favorite langage. So he will do it in the language he knows. It could have been VHDL only with another author


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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@borinsky In the very first version xapp1097 1.0 (Oct 2013), it used to have both code files : VHDL and Verilog. It was for ISE based design at that time.

 

There were some issues using VHDL files so it was dropped, but I couldn't remember the exact issue. Anyway, VHDL shouldn't be mentioned in the current xapp1097.

 

I don't think there is a plan to supply VHDL for xapp1097

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Newbie borinsky
Newbie
2,055 Views
Registered: ‎02-15-2018

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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Since my project is in VHDL that means the SDI and GTP cores are generated in VHDL. So I will end up with Verilog wrappers round VHDL cores. Plus a VHDL project that includes a large lump of Verilog. Is this VHDL within Verilog within VHDL structure likely to cause any problems?

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Moderator
Moderator
2,048 Views
Registered: ‎11-09-2015

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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Hi @borinsky,

 

No you can have a mixed of verilog and VHDL


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar drjohnsmith
Scholar
2,726 Views
Registered: ‎07-09-2009

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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I have no probelm with the core being what ever language Xilxin want.

 

But till recently, Xilinx supported both verilog and VHDL , and provided verilog wrappers for vhdl and verilog wrappers for vhdl.

 

Now if its a verilog core, no more a vhdl wrapper, 

  

Come on now.

 

If a wrapper is easy, then you can knock it out quickly and support it,

 

If a wrapper is hard, then not providing one , puts the none supported language at a significant disadvantage.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Newbie borinsky
Newbie
1,035 Views
Registered: ‎02-15-2018

Re: XAPP1097 SDI interface - where are the VHDL wrappers?

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So if I want to instantiate a Verilog module in a VHDL design I think I need to wrap it in a VHDL entity/architecture structure.

Like shown here and quoted below: http://vhdlguru.blogspot.co.uk/2012/06/how-to-mix-vhdl-and-verilog-files-in.html This seems to show the Verilog module instantiated twice. To keep things clean I think I would simply wrap VHDL round each Verilog module so I can use it just as if it was VHDL.

 

 



library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity test is port( Q : out std_logic_vector(1 downto 0); D :in std_logic_vector(3 downto 0) ); end test; architecture Behavioral of test is component a1 is port( Q : out std_logic; D :in std_logic_vector(1 downto 0) ); end component; begin a11 : a1 port map(Q(0),D(1 downto 0)); a22 : a1 port map(Q(1),D(3 downto 2)); end Behavioral;
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