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Visitor alfa_hw
Visitor
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Registered: ‎07-14-2017

XAPP894 w MIPI D-PHY LogiCORE

Hi All,

I would like to know what is the maximum expected bandwidth per lane implenting the design solution shown in the XAPP894 with the MIPI D-PHY LogicCORE v4.1 on a Zynq 7000 XC7z020clg484 board for a chip to chip communication (sensor and FPGA are on the same board).

I see in the XAPP894 (v1.0) August 25, 2014 documentation, pag15,  is declared a maximum comunication bandwitdh of 800Mb/s while in the PG202 (v4.1) July 2, 2019 MIPI D-PHY LogicCORE, pag14 table2, is stated a maximum bandwidth 1250Mb/s (7 series).

What is the real performance in this case?

Thanks

Fabio

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Moderator
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Registered: ‎10-04-2017

Re: XAPP894 w MIPI D-PHY LogiCORE

Hi @alfa_hw,

As you mention XAPP894 is dated 2014. This means that the core used was not V4.1, but I believe V1.0.

You can check version information in the Master AR for the IP. This can be found in the IP facts page of the PG.

2020-01-22 06_50_17-Xilinx Documentation Navigator 2019.2 - file____C__Users_samk_Documents_XilinxDo.png2020-01-22 06_51_42-AR# 54550_ LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivad.png

So your answer is really dependent on which version of the tools you are using. If you are in the 2019.2 version of Vivado, the core has been tested up to 1250MBps for 7-series but can allow faster speeds and up to 2.5Gbps for newer devices.

**We have a Spartan-7 design for MIPI CSI-2 which uses the D-PHY. See chapter 5 of PG232.

 

 

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