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Registered: ‎06-18-2013

Xilinx CoregenMacc Latency mismatch



I instantiate a multiply accumulator in my design. The multiply accumulator is generated by core generator. When generating the core I set the latency as 2 while after generating the core I found that the actual latency inside of this core is 6.Could you help me to find that why the latency I set when generating the core is different from the actual latency?


1.I attached my design project,file name is project.
2.The coregen settings are as pic corgen.PNG
3.To verify the latency you can use the ISIM simulation project, there is also a testbench in my design folder to help you find the actual latency.
4.To verify the latency you also could watch the internal structure of generated core by planahead as pic planahead.PNG, you can find every latency of DSP48 by watching the attribute of DSP48 as pic attribute.PNG to help you calculate the generated core's total latency.


I implemented my design on Kintex7 device. ISE14.4.





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