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440 Views
Registered: ‎01-14-2019

Xilinx DisplayPort RX Subsystem v2.1 - Core Problems

Hello,

we are trying to integrate in our FPGA kintex-7 XC7K70T-1 the Xilinx DisplayPort RX Subsystem v2.1 to receive a  DP1.2 flow. (the application requires to send the flow to two MiniDisplays). We have designed the board from scratch, we are able to switch on and off the display, we are able to send some patterns internally generated within the FPGA to the displays ...everything is ok. But we have some problems in acquiring the DP data from the source(we do not have the Xilinx eval board and mezanine required to try the DP macro).

We are working with a 1600x1200@60fps RGB 24bit, even if the target is we are working with a 3200x1200@120fps RGB 24bit

 

Currently we are in this situation:

we started from the reference design xdprxss_kc705 which implements both TX and RX on kintex7 and removed the TX part.

now we are able to connect our board to a linux PC or to a windows one using a standard DP cable and we obtain always the stable link (i.e we always receive the requested Vblanks).

Then by adding in the code a reset command dprx_resetvideooutput we have been able to receive the correct control signals from DP_RX native video outptu (i.e. VSYNC, HSYNC and DE). These signals are correctly powering up the Displays: in fact if we replace pixel data from DP_RX with a fixed white pixel generated inside the FPGA to the Displays, we are able to see both the displays switched on and showing a totally white image.

But if we connect again pixel data from the DP macro instead of the fixed-white pixel, the output is black (i.e. pixel data equal to 0). We suspect we have to somehow enable the stream on them using some specific commands but we have not been able to find them in the reference design. Should we exec any other commands after dprx_ResetVideoOutput to enable pixel data?

Can someone support us? we are in a hurry since we have a deadline quite close and we need to have the working flow ...

Thanks a lot in advance

Bye

Giovanna

 

 

 

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8 Replies
Scholar watari
Scholar
393 Views
Registered: ‎06-16-2013

Re: Xilinx DisplayPort RX Subsystem v2.1 - Core Problems

Hi @giovanna.ferrara 

 

I suspect some wrong points.

But it is not enough information to clear the route cause.

 

Could you tell me in more detail about video signal ?

Especially, DP lane, HTOTAL, VTOTAL, Pixel clock frequency and color depth.

 

Also, I ask you the following.

 

- When you get black video signal on DP Rx, what value does it set on black video enable register ?

=> I suspect you use DP as like eDP.

 

- When you get black video signal on DP Rx, how about HPD signal is it ?

 

Best regards,

374 Views
Registered: ‎02-27-2019

Re: Xilinx DisplayPort RX Subsystem v2.1 - Core Problems

Hi @watari,

I am a @giovanna.ferrara's colleague.

Actual configured modeline is:

`Modeline "1600x1200" 148.5 1600 1752 1768 1800 1200 1334 1339 1375 +hsync +vsync`

HTOTAL=1800
VTOTAL=1375
Pixel Clock=148.5MHz
ColorDepth=RGB 8:8:8

About "black video enable register", I'm not able to find a register like this, could you please provide a specific offset of DP_RX register map?

About the DP link, all seems to be good. From microblaze log the connectios is stable, and also DP source see DP sink correctly connected and in use.

Best regards,

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Scholar watari
Scholar
334 Views
Registered: ‎06-16-2013

Re: Xilinx DisplayPort RX Subsystem v2.1 - Core Problems

Hi gabriele.sorrenti@sanitaseg.it 

 

I'd like to clarify my understanding.

 

- 1600x1200@60Hz -> A part of target resolution

- 3200x1200@120Hz -> Primary target resolution

- (Maybe) eye is fine. But not clear link rate. (<-Q1)

- DP Source doesn't use like "black video enable" function.

  => Basically, DP Source set this value on DPCD. But it's eDP function.

 

If my understanding is correct, could you tell me the followings ?

 

Q1) How many lane do you use ? Also what link rate do you use ?

Q2) How do you deal with native video timing controller ?

Q3) Which type do you use, using frame buffer or non frame buffer ?

Q4) Can you follow VESA CVT formura ?

Q5) If possible, could you share the source device name or source device categoly (GPU or custom DP Tx or other)?

 

Best regards,

311 Views
Registered: ‎02-27-2019

Re: Xilinx DisplayPort RX Subsystem v2.1 - Core Problems

R1) 4 lane, in this configuration Source and Sink negotiate 2.7Gbps per lane

R2) I didn't configure native timing controller in any way, only give dprx_ResetVideoOutput command after DP link is established. I suppose it is configured autonomously according to DCPD configuration received. is it correct?

R3) I removed VDMA frame buffer from DisplayPort example design because we don't have DDR. I know I need to manage this with a FIFO but the problem is I don't see activity on pixel signal at all. I also tried to change DP_RX output from Native to AXI4-stream but I cannot obtain any activity on the output of "AXI4-stream to Video Output" connected to DP_RX even if this part of design is already validated because AXI4-stream to video output" and Video Timing Generator works fine with Video Pattern generato instead of DP_RX as source.

R4) Please clarify, sorry, I doesn't understand the question.

R5) We are using two different devices as DP source:
- Linux (Debian 8) workstation hosting NVIDIA GPU with native DisplayPort output
- Windows 7 Dell laptop with DisplayPort on docking station

It should be notice that I reuse EDID provided from Micro Oled Display Evaluation Board (HDMI based). Could this point be relevant to "black video enable " of eDP?

Best regards

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297 Views
Registered: ‎02-27-2019

Re: Xilinx DisplayPort RX Subsystem v2.1 - Core Problems

I found an evidence that pixels are synplified to GND on synthesis, trying to insert an ILA. It's not clear why.

Cattura.PNG

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Scholar watari
Scholar
275 Views
Registered: ‎06-16-2013

Re: Xilinx DisplayPort RX Subsystem v2.1 - Core Problems

Hi gabriele.sorrenti@sanitaseg.it 

 

R2)

A little different. It is configured autonourmously according msa and vbid field in DP packet.

It is decoded by DP sink.

 

R3)

Can you observe generated pixel clock by Oscilloscope ?

I suspect this quality.

 

R4)

Would you refer the following URL ?

 

https://en.wikipedia.org/wiki/Coordinated_Video_Timings

 

R5)

Sorry. In this case, it is not relevant to "black video enable".

BTW, I suspect this EDID value, too.

Because it is relevant to CEA video timing. However "Htotal" and "Vtotal" are different it.

Would you follow VESA CVT video timing, even if your video timing is custom ?

 

Best regards,

250 Views
Registered: ‎01-14-2019

Re: Xilinx DisplayPort RX Subsystem v2.1 - Core Problems

Hello watari,

Gabriele has been able solving the issue, including a ila core in the design to debug (I do not have details in this moment).

Thanks for your interest in our problem

regards

Giovanna

Adventurer
Adventurer
234 Views
Registered: ‎10-03-2018

Re: Xilinx DisplayPort RX Subsystem v2.1 - Core Problems

Hello @giovanna.ferrara,

I'm glad you've resolved the problem. 

Are you able to tell us what the solution was? 

Kind Regards,
Peimann, S. M.
----
Toddlers are the Storm-Troopers of the Great God Entropy.
Physics: Not Just a Good Idea, It's THE LAW.
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