UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
523 Views
Registered: ‎06-20-2018

Xilinx I2S IP

I am using Xilinx I2S IP. I am trying to transfer the Data written in DDR to I2S via CDMA IP. But the DMA axi stream interface does not have TID control bit which is required by the I2S IP. IF i dont provide TID, the IP doesnot work. I am using 24 bit, 2 channel for I2S. Let me know what can be done for TID.

0 Kudos
2 Replies
Moderator
Moderator
488 Views
Registered: ‎11-09-2015

Re: Xilinx I2S IP

Hi @raghusrinivas451993,

I believe you will need to write your own logic to control the TID. If you are sending only to 2 channel and you are switching for each data, it is quite easy. You just need to toggle the TID bit each time you have tready and tvalid = 1.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
443 Views
Registered: ‎11-09-2015

Re: Xilinx I2S IP

HI @raghusrinivas451993,

Do you have any updates on this? Was my reply enough for you?

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos