UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer laurencebarker
Observer
1,820 Views
Registered: ‎05-27-2018

Xilinx I2S IP

Jump to solution

My design will use an Artix 7 FPGA with a TLV320AIC23B codec. the TLV32 has both ADC and DAC, and has a common bit clock (BCLK on the data sheet). Xilinx provide separate I2S transmitter and receiver cores, each of which generates an SCK bit clock signal. For both to work, the SCK signals would need to have the same phase.

 

is there any way to synchronise the TX and RX cores so that I can use SCK from one core to the TLV320 please?

0 Kudos
1 Solution

Accepted Solutions
Observer cbanvill
Observer
1,153 Views
Registered: ‎05-23-2018

Re: Xilinx I2S IP

Jump to solution

The I2S transmitter and receiver can be configured to be master or slave with regards to the clock signals. However, this option is not present in the configuration GUI.

To change an I2S core configuration to slave (master is the default), select the core in the BD diagram, go to the 'Block Properties' Window, click on the 'Properties' tab, expand the CONFIG property and set the C_IS_MASTER property to 0.

If you are not using an IPI BD, go to the Source->IP Sources tab and select the IP that you want to modify. Then follow the same instructions in the 'Source File Properties' Window.

I2S_config.png

 

8 Replies
Visitor ozatarain
Visitor
1,665 Views
Registered: ‎03-23-2017

Re: Xilinx I2S IP

Jump to solution

I also have the same problem, did you find a way to synchronize the TX and RX cores? 

0 Kudos
Newbie becky298
Newbie
1,461 Views
Registered: ‎09-07-2018

Re: Xilinx I2S IP

Jump to solution

@ozatarain wrote:

I also have the same problem, did you find a way to synchronize the TX and RX cores? 


Well, I am still finding the solution. Same problem :( 

0 Kudos
Observer cbanvill
Observer
1,154 Views
Registered: ‎05-23-2018

Re: Xilinx I2S IP

Jump to solution

The I2S transmitter and receiver can be configured to be master or slave with regards to the clock signals. However, this option is not present in the configuration GUI.

To change an I2S core configuration to slave (master is the default), select the core in the BD diagram, go to the 'Block Properties' Window, click on the 'Properties' tab, expand the CONFIG property and set the C_IS_MASTER property to 0.

If you are not using an IPI BD, go to the Source->IP Sources tab and select the IP that you want to modify. Then follow the same instructions in the 'Source File Properties' Window.

I2S_config.png

 

Moderator
Moderator
1,118 Views
Registered: ‎11-09-2015

Re: Xilinx I2S IP

Jump to solution

Hi @cbanvill,

Thank you for sharing your solution to get the slave mode. I have only one clarification for add: The slave mode is not yet supported by Xilinx. The user is responsible for its characterization. In fact this is the reason one the option is hidden from the GUI.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Observer cbanvill
Observer
1,099 Views
Registered: ‎05-23-2018

Re: Xilinx I2S IP

Jump to solution

Hi Florent,

Thank you for the clarification. This is a bit surprising since the I2S receiver core example design is using the slave mode!

Regards,

0 Kudos
Moderator
Moderator
982 Views
Registered: ‎11-09-2015

Re: Xilinx I2S IP

Jump to solution

Hi @cbanvill,

I completely agree. I already made the same comment to development.

From my point of view, if it is used in the example design it should be supported. Thus I already requested to get official support.

However, the current status is as per the Product Guide for the IP. I.e. The core in Slave mode is not supported yet.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Moderator
Moderator
923 Views
Registered: ‎11-09-2015

Re: Xilinx I2S IP

Jump to solution

Hi @laurencebarker,

Is everything clear for you on this subject?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Observer laurencebarker
Observer
909 Views
Registered: ‎05-27-2018

Re: Xilinx I2S IP

Jump to solution

I've clicked "accept as solution" but I had by then written Verilog code to provide an I2S interface. I would have preferred catalogue IP, but I got there.