11-14-2018 12:42 AM
I am using Xilinx I2S IP. I am trying to transfer the Data written in DDR to I2S via CDMA IP. But the DMA axi stream interface does not have TID control bit which is required by the I2S IP. IF i dont provide TID, the IP doesnot work. I am using 24 bit, 2 channel for I2S. Let me know what can be done for TID.
11-15-2018 02:45 AM
I believe you will need to write your own logic to control the TID. If you are sending only to 2 channel and you are switching for each data, it is quite easy. You just need to toggle the TID bit each time you have tready and tvalid = 1.
11-23-2018 05:57 AM
Do you have any updates on this? Was my reply enough for you?
Thanks and Regards,