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Visitor yolin88
Visitor
251 Views
Registered: ‎11-24-2018

Xilinx Zynq 7 Series MIPI D-PHY question.

Hi,

  I am reading Xapp894-d-phy-solutions (XAPP894 v1.0) Figure10 and 11 shows the IO standard as LVCMOS18_F_8_HP, DIFF_HSTL_I_18_F.., HSUL_12_S_HR, LVDS_25_HR_I_P

I plan to use it for my MIPI external D-PHY solution. my application is to drive a 800x480 pixel MIPI LCD (2-lane). 

Question 1: Can XC7Z007S, XC7Z014S, XC7Z010, XC7Z0020 support the IO listed above?

Question 2: If all IOs are used above, do I need 1.8V, 1.2V, 2.5V power source all together? Please let me know the banks I need to assign for each voltage. 

Question 3. Can I settle with 2 voltages only? 1.8V LVDS. I have on board 3.3V logic. I need to use 3.3V as the source. Converting to 1.2V, 1.8V and 2.5V is too much of cost. Any suggestions?

 

Thanks,

 

Philip

 

 

 

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10 Replies
Xilinx Employee
Xilinx Employee
215 Views
Registered: ‎03-30-2016

Re: Xilinx Zynq 7 Series MIPI D-PHY question.

Hello Philip  @yolin88

1. I would suggest to use UltraScale+ devices since MIPI D-PHY signal is natively supported by HP I/O.
   No need for external devices if you are using UltraScale+ device. This is Xilinx best solution for MIPI.
2. If your application requires 7-series devices, please consider to use external PHY devices.
   For example : Device solution from Meticom. ( http://meticom.com/page2/page20/MC20902.html )
3. If your 7-series evaluation system has FMC connector on-board, You might also consider external board solution from our partner.
   https://solutions.inrevium.com/products/pdf/TB_FMCL_MIPI_HWUserManual_3.01e.pdf
   https://www.xilinx.com/products/boards-and-kits/1-d2cwd1.html

Some inputs for your questions.  
A1. Yes. LVCMOS18, DIFF_HSTL_I_18, HSUL_12, LVDS_25 are supported by HR I/O banks.
Please see DS187 page 11-13.
https://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf

Please be careful that some small package only has some unbonded I/Os. (Please see UG865 Chapter1)
https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf

A2.
Yes.Please see UG471 chapter 1 for Vcco requirement.
But, if you want to use MIPI DSI TX Subsystem to drive MIPI LCD then you only need 1.8V as mentioned by XAPP894 Figure10.

A3. I do not know. Since this is an XAPP, You are free to play and try some experiment.

Regards,
Leo

Visitor yolin88
Visitor
197 Views
Registered: ‎11-24-2018

Re: Xilinx Zynq 7 Series MIPI D-PHY question.

Hi Leo,

    Since LANE0  is bi-directional, I might need to implement both TX (Figure 10) and RX (Figure 11).

 May need to provide 2.5V for RX.

Can LVDS bank use 1.8V (Figure 11)? If not, I guess the following example is my best hope.

Example (Xc7z007sclg225):  I may need to assign 1.8V (TX) to Bank 34, and 2.5V (RX) to Bank 35. There only Bank34, 35 for HR IOs. Is this correct?

Philip

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Xilinx Employee
Xilinx Employee
191 Views
Registered: ‎03-30-2016

Re: Xilinx Zynq 7 Series MIPI D-PHY question.

Hello Philip @yolin88

Using US+ devices or Compliant solution ( from Meticom or Inverium) are your best options.

BTW, I am assuming you want to use MIPI DSI TX Subsystem. Please see "Unsupported Features" mentioned in PG238 and PG202.
Unfortunately, Xilinx MIPI IP does not support Link turnaround ( or Bi-directional IO ).
Please note that the latest (from Vivado 2018.2) MIPI DSI TX Subsystem does not support DCS Long write or DCS read command. We do have a plan to enhance our MIPI DSI TX Subsystem, but we cannot commit any release date at a moment.

If your  MIPI LCD requires DCS Long write or DCS read command, please try to find another MIPI IP solution.

Thanks & regards
Leo

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Visitor yolin88
Visitor
179 Views
Registered: ‎11-24-2018

Re: Xilinx Zynq 7 Series MIPI D-PHY question.

I can't use UltraScale for now due to the cost model.

Let me confirm with the vendor to see if DCS Long write or DCS read commands are needed.

 

Visitor yolin88
Visitor
160 Views
Registered: ‎11-24-2018

Re: Xilinx Zynq 7 Series MIPI D-PHY question.

Hi Leo,

   Got confirmation from the LCD vendor. LCD driver can run without bi-direction. But they need Data Type = 0x39/0x29 for long packets.

   You mentioned Zynq Ultrascale+ doesn't have this problem. This means it is supporting Long Packet (Read/Write) and Bidirectional, right?

I might need to abandon the Xilinx solution if I can't make Zynq 7000 to work. Can you please double check one more time to see if the Long packets can be supported in the coming 1-2 months? 

Thanks,

Philip

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Xilinx Employee
Xilinx Employee
147 Views
Registered: ‎03-30-2016

Re: Xilinx Zynq 7 Series MIPI D-PHY question.

Hello Philip @yolin88

>You mentioned Zynq Ultrascale+ doesn't have this problem. This means it is supporting Long Packet (Read/Write) and Bidirectional, right?

No, Xilinx MIPI DSI-TX Subsystem IP itself does not support :
     - DCS Long Packet (Read/Write)
     - Link turnaround / Bi-directional IO.
(It is not related with the device used )

Please see AR#71336. Long Packet write is not supported.
  https://www.xilinx.com/support/answers/71336.html
  XF_AR71336.png
  Note that DCS read command is also not supported. This AR is already fixed internally. (It will be live soon)
 
Please see also PG238.  (Unsupported Features)
  https://www.xilinx.com/support/documentation/ip_documentation/mipi_dsi_tx_subsystem/v2_0/pg238-mipi-dsi-tx.pdf

I suggest you to use UltraScale+ devices since it has native I/O support for MIPI D-PHY.
It will save you time tuning the resistor-network for your board.

>Can you please double check one more time to see if the Long packets can be supported in the coming 1-2 months?

Confirmed the milestone. IP enhancement is scheduled for Vivado 2019.2 but we cannot make any commitment at this moment.

If you have a local Xilinx FAE that support your current project.
Please ask your Xilinx FAE to contact Technical Marketing, ask whether we can prioritize/accelerate this MIPI IP enhancement  schedule for you.

Thanks & regards
Leo

Visitor yolin88
Visitor
100 Views
Registered: ‎11-24-2018

Re: Xilinx Zynq 7 Series MIPI D-PHY question.

This answer basically tells me the Xilinx IP doesn't work for MIPI DSI applications.

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Xilinx Employee
Xilinx Employee
74 Views
Registered: ‎03-30-2016

Re: Xilinx Zynq 7 Series MIPI D-PHY question.

Hello Philips @yolin88

We apologize for the inconvenience caused.
Yes, unfortunately your understanding is correct. It will not work if your MIPI Display requires DCS long write.
(PG238 already mentioned that only Type4 Architecture is supported)

I am trying to push this request to our developer team, and I hope it can jump into 2019.1 release ( or even faster. But not 1-2 months as your expectation ).
I understand that Long Packet length may up to 64K bytes as mentioned by DCS spec.
But just for my reference, Could you please tell me how many byte Long Packet is requiered for your MIPI display to use all of its functionality ?
I am wondering if a packet-lenght limitation could accelerate this request.

BTW, there is also 3rd Vendor MIPI IP. (I've never use the IP though)
You may want to check if this IP supports DCS long-write.
https://nwlogic.com/products/mipi-solution/
https://nwlogic.com/products/docs/DSI_Controller_Core.pdf

Thanks & regards
Leo

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Visitor yolin88
Visitor
69 Views
Registered: ‎11-24-2018

Re: Xilinx Zynq 7 Series MIPI D-PHY question.

Please do not point people to NW Logic. I got the response from them stating that they are getting out of FPGA business. Focused on ASIC IP only. 

The long packets size I can tell is only less than 10-20 bytes for initializing the IC driver. It shouldn't be like in KB size.

 

Philip

Xilinx Employee
Xilinx Employee
40 Views
Registered: ‎03-30-2016

Re: Xilinx Zynq 7 Series MIPI D-PHY question.

Thank you very much for the information @yolin88

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