04-12-2019 05:52 AM
My native video input is 40 bit YCbCr , It would be helpful if anyone could help me in converting 40 bit YCbCr to a 32 Bit YCbCr.
Because my custom logic require YCbCr 32 bit input .
Please guide me to remove the extra bit from the 40Bit YCbCr.
04-14-2019 11:40 PM
Can you give more details about your complete video pipeline or at least around the receiver side which IP you have to accept this YCbCr data from the video source inside Xilinx FPGA?
Maybe with that input, we can help you better.
04-14-2019 11:51 PM
I guess your current native video is YUV 4:2:2 as color depth 10bit and 2[pixel/clock].
Also, your target video format is YUV 4:2:2 as color depth 8bit and 2[pixel/clock].
Is my understanding correct ?
If yes, you only disconnect 2bit of lsb.
04-15-2019 04:44 AM
Hi @kvasantr ,
Thanks for the Replying.
The input video is from the SDI and then it is stored to the DDR and I want to take the input from the Display Port
A simple block diagrm for the same
So I have 10 bit input as 2 pixel/clock rom the SDI IP that will be 40 bit for YCbCr so for my custom logic I want 32 bit YCbCr. That I can store in DDR and display on Display port.
04-15-2019 06:12 AM
04-18-2019 12:42 AM
Do you have any updates on this? Is everything clear for you?
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