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Visitor uuoo93
Visitor
711 Views
Registered: ‎09-12-2018

ZCU102, ‘MIPI CSI-2 RX subsystem IP example design’ problems on vivado 2018.2

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Hello. I am working on Zynq UltraScale+ ZCU102 Evaluation Board and Vivado HLx system suite version 2018.2.(Window O.S) I was trying to open ‘MIPI CSI-2 Rx subsystem IP example design’ and it was successful until ‘Block Design’ was generated as shown in Figure 1 below. figure 1.png

<Figure 1>

However, I faced the problem when trying ‘Run Synthesis’ as shown in Figure 2 below.

figure 2.png

<Figure 2>

How can I solve this problem?

1 Solution

Accepted Solutions
Moderator
Moderator
695 Views
Registered: ‎11-09-2015

Re: ZCU102, ‘MIPI CSI-2 RX subsystem IP example design’ problems on vivado 2018.2

Jump to solution

Hi @uuoo93,

This is a path length issue. You might want to generate the example design at the root directory of your drive.

You can also apply the same steps as mentioned in AR#70328 (adapt it for MIPI).

Note that the path lenght should be reduced in the example design for 2018.3

Hope that helps,

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
1 Reply
Moderator
Moderator
696 Views
Registered: ‎11-09-2015

Re: ZCU102, ‘MIPI CSI-2 RX subsystem IP example design’ problems on vivado 2018.2

Jump to solution

Hi @uuoo93,

This is a path length issue. You might want to generate the example design at the root directory of your drive.

You can also apply the same steps as mentioned in AR#70328 (adapt it for MIPI).

Note that the path lenght should be reduced in the example design for 2018.3

Hope that helps,

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**