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Observer sigan
Observer
187 Views
Registered: ‎05-28-2019

ZCU102 Rev 1.0 ES2 | Memory write error at 0x0. Blocked address 0x0. DDR controller is not initialized

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Hi, I'm trying to run Passthrough HDMI example software on a ZCU102 Rev 1.0 ES2 board from the SDK bundled in the Vivado 2018.3 design suite. Running from xsdb via the Vivado 2018.1 Tcl Shell trying to run the Passthrough_A53 software this error shows up: "Memory write error at 0x0. Blocked address 0x0. DDR controller is not initialized".

Dump from xsdb terminal follows.

xsdb% fpga -file ./v_hdmi_rx_ss_0_ex.runs/impl_1/exdes_wrapper.bit
100% 25MB 1.7MB/s 00:15
xsdb%
xsdb% ta
1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU (L2 Cache Reset)
9* Cortex-A53 #0 (APU Reset)
10 Cortex-A53 #1 (APU Reset)
11 Cortex-A53 #2 (APU Reset)
12 Cortex-A53 #3 (APU Reset)
xsdb% dow ./v_hdmi_rx_ss_0_ex.sdk/standalone_bsp_0_Passthrough_A53_1/Debug/standalone_bsp_0_Passthrough_A53_1.elf

Failed to download C:/projects/fpga/hdmi_ip_core_example_proj/v_hdmi_rx_ss_0_ex/v_hdmi_rx_ss_0_ex.sdk/standalone_bsp_0_Passthrough_A53_1/Debug/standalone_bsp_0_Passthrough_A53_1.elf
APU L2 cache is held in reset
xsdb% rst -processor
Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)
xsdb% dow ./v_hdmi_rx_ss_0_ex.sdk/standalone_bsp_0_Passthrough_A53_1/Debug/standalone_bsp_0_Passthrough_A53_1.elf
Downloading Program -- C:/projects/fpga/hdmi_ip_core_example_proj/v_hdmi_rx_ss_0_ex/v_hdmi_rx_ss_0_ex.sdk/standalone_bsp_0_Passthrough_A53_1/Debug/standalone_bsp_0_Passthrough_A53_1.elf
section, .text: 0x00000000 - 0x00029c03
section, .init: 0x00029c40 - 0x00029c73
section, .fini: 0x00029c80 - 0x00029cb3
section, .note.gnu.build-id: 0x00029cb4 - 0x00029cd7
section, .rodata: 0x00029cd8 - 0x000324df
section, .rodata1: 0x000324e0 - 0x000324ff
section, .sdata2: 0x00032500 - 0x000324ff
section, .sbss2: 0x00032500 - 0x000324ff
section, .data: 0x00032500 - 0x00033d97
section, .data1: 0x00033d98 - 0x00033dbf
section, .ctors: 0x00033dc0 - 0x00033dbf
section, .dtors: 0x00033dc0 - 0x00033dbf
section, .eh_frame: 0x00033dc0 - 0x00033dc3
section, .mmu_tbl0: 0x00034000 - 0x0003400f
section, .mmu_tbl1: 0x00035000 - 0x00036fff
section, .mmu_tbl2: 0x00037000 - 0x0003afff
section, .preinit_array: 0x0003b000 - 0x0003afff
section, .init_array: 0x0003b000 - 0x0003b007
section, .fini_array: 0x0003b008 - 0x0003b047
section, .sdata: 0x0003b048 - 0x0003b07f
section, .sbss: 0x0003b080 - 0x0003b07f
section, .tdata: 0x0003b080 - 0x0003b07f
section, .tbss: 0x0003b080 - 0x0003b07f
section, .bss: 0x0003b080 - 0x0003cf3f
section, .heap: 0x0003cf40 - 0x0003cf3f
section, .stack: 0x0003cf40 - 0x0003ff3f
aborting, 1 pending requests...
Failed to download C:/projects/fpga/hdmi_ip_core_example_proj/v_hdmi_rx_ss_0_ex/v_hdmi_rx_ss_0_ex.sdk/standalone_bsp_0_Passthrough_A53_1/Debug/standalone_bsp_0_Passthrough_A53_1.elf
Memory write error at 0x0. Blocked address 0x0. DDR controller is not initialized

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1 Solution

Accepted Solutions
Observer sigan
Observer
117 Views
Registered: ‎05-28-2019

Re: ZCU102 Rev 1.0 ES2 | Memory write error at 0x0. Blocked address 0x0. DDR controller is not initialized

Jump to solution

Hi, solved this issue by building a new FSBL with patch from Xilinx and downloading it to target prior to downloading the application software.

See this link on how to build FSBL with patch: https://www.xilinx.com/support/answers/72113.html

Other useful link: https://www.xilinx.com/support/answers/71961.html

If you are experiencing the same problem as me with the ZCU102 Rev 1.0 ES2 (ES2 = engineering sample device) try doing this:
1) Create a new FSBL project in Xilinx SDK and build with the updated files, follow link above.
2) Select JTAG as boot mode on SW6.
3) Program FPGA from SDK.
4) Download FSBL from SDK.
5) Download target application from SDK.

1 Reply
Observer sigan
Observer
118 Views
Registered: ‎05-28-2019

Re: ZCU102 Rev 1.0 ES2 | Memory write error at 0x0. Blocked address 0x0. DDR controller is not initialized

Jump to solution

Hi, solved this issue by building a new FSBL with patch from Xilinx and downloading it to target prior to downloading the application software.

See this link on how to build FSBL with patch: https://www.xilinx.com/support/answers/72113.html

Other useful link: https://www.xilinx.com/support/answers/71961.html

If you are experiencing the same problem as me with the ZCU102 Rev 1.0 ES2 (ES2 = engineering sample device) try doing this:
1) Create a new FSBL project in Xilinx SDK and build with the updated files, follow link above.
2) Select JTAG as boot mode on SW6.
3) Program FPGA from SDK.
4) Download FSBL from SDK.
5) Download target application from SDK.