cancel
Showing results for 
Search instead for 
Did you mean: 
Scholar
Scholar
5,229 Views
Registered: ‎11-09-2013

ZCU102, Zynq MPSoC DisplayPort clocking

Jump to solution

trying again with more specific problem, ZCU102 TRD uses si570 as DP clock in devicetree, this clock is not used in hardware but it can not be removed from devicetree, so what is the solution?

 

if we wand the si570 to be use for other clock then DP, how should we then decribe Xilinx DP DRM in devicetree?

 

DP itself works, both in 1 lane and 2 lane configurations, pretty cool

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar
Scholar
9,461 Views
Registered: ‎11-09-2013

Re: ZCU102, Zynq MPSoC DisplayPort clocking

Jump to solution

problem identified workaround implemented.

 

waiting for the FIX, 2016.3 ? or 2016.4 well need wait and hope..

View solution in original post

0 Kudos
2 Replies
Highlighted
Scholar
Scholar
5,161 Views
Registered: ‎11-09-2013

Re: ZCU102, Zynq MPSoC DisplayPort clocking

Jump to solution

Partially solved, we have succesfully removed si570 entry from devicetree and still have picture on DisplayPort monitor

0 Kudos
Highlighted
Scholar
Scholar
9,462 Views
Registered: ‎11-09-2013

Re: ZCU102, Zynq MPSoC DisplayPort clocking

Jump to solution

problem identified workaround implemented.

 

waiting for the FIX, 2016.3 ? or 2016.4 well need wait and hope..

View solution in original post

0 Kudos