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Observer ankitsohni
Observer
711 Views
Registered: ‎07-31-2018

ZCU106 - 64 bit DDR4 Component Memory interfaced with PL

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 Evaluation Kit design (zcu106) :   16 bit DDR4 Component (4 Nos) is being utilized as single 64 bit DDR4 Memory where address lines and control signals are shared among all of the four 16 bit DDR4 memory to make it as single 64 bit DDR4. Where this 64 bit DDR4 memory is being utilized in software segment? whether it is being used as Frame buffer for passing data between Video Codec Unit(VCU) Core and DDR4. If it is so? can it be achieved with 32 bit DDR4 memory.

Interface for Dual 32 bit DDR4 memory in customized design : Considering the HP I/O banks are available in PL, is it possible to have interface for Dual 32 bit DDR4 memory in the design. where DDR4 Mem-1(32 bits) & DDR4 Mem-2(32 bits) will be having two separate  address and control signals. In this case, which HP I/O banks should be preferred to route address and control signals for Mem-1 and Mem-2 ?

In this scenario, whether 32 bit DDR4 would be sufficient to data transfer between VCU and DDR4.

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Xilinx Employee
Xilinx Employee
637 Views
Registered: ‎08-01-2007

Re: ZCU106 - 64 bit DDR4 Component Memory interfaced with PL

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The 2018.3 includes a new VCU DDR4 Controller that can be used with the ZCU106.  You can find the documentation for the VCU DDR4 Controller included in PG252.  This will also give you information on how to enable the VCU DDR4 Controller with the VCU in the 2018.3 ZCU106 PetaLinux BSP.  by making the necessary changes to the Device Tree.

Chris
Video Design Hub | Embedded SW Support

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2 Replies
Xilinx Employee
Xilinx Employee
638 Views
Registered: ‎08-01-2007

Re: ZCU106 - 64 bit DDR4 Component Memory interfaced with PL

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The 2018.3 includes a new VCU DDR4 Controller that can be used with the ZCU106.  You can find the documentation for the VCU DDR4 Controller included in PG252.  This will also give you information on how to enable the VCU DDR4 Controller with the VCU in the 2018.3 ZCU106 PetaLinux BSP.  by making the necessary changes to the Device Tree.

Chris
Video Design Hub | Embedded SW Support

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Moderator
Moderator
567 Views
Registered: ‎11-09-2015

Re: ZCU106 - 64 bit DDR4 Component Memory interfaced with PL

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Hi @ankitsohni,

Was the reply from @chrisar enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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