UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
2,089 Views
Registered: ‎06-13-2018

ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

I have what looks like a D-Phy termination problem with my use of the MIPI CSI-2 RX Subsystem. 

 

I have a TI DS90UB954 Deserializer receiving camera sensor data.  The Deserializer has a CSI-2 driving a 4 lane CSI-2 input to a ZU3EG.  I took two scope shots of the interface.  The first scope shot is with the FPGA not loaded.  The second shot is with the FPGA loaded.  You can see from the CsiInputUnloadedFPGA shot that the signals look reasonable since there are no sync terminations to pull the line high during the Low Power portion of the waveform.

 

CsiInputUnloadedFPGA.jpg

 

I expected to see the Low Power portion of the waveform to be up at 1.2volts or so when I loaded the FPGA with the MIPI CSI-2 RX Subsystem IP but instead I got what you see in the second image (CsiInputLoadedFPGA). 

 

CsiInputLoadedFPGA.jpg

 

This looks to me like the I/O of the DPHY is not transistioning correctly between the Long HS packets and the Low Power modes.  Does anyone have any idea on why this may be the case or do you have another explanation for what I am seeing?

 

thanks,

david

0 Kudos
1 Solution

Accepted Solutions
2,127 Views
Registered: ‎06-13-2018

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hi Leo,

 

I said I would get back with you once I got my SERDES CSI-2 clock going and this final post in in regard to that.  I was able to get the clock going and the signal levels all straightened out and that allowed the IP block to get initialized and I was able to see that it was getting data using the "Jtag to Axi" IP block.  I wasn't getting anything out of the data port initially but I realized that the VFB block was rejecting my packets for various reasons.  I removed that I was able to see data.  I still have some work to do in regard to cleaning the stream up but things seems to be working at this point.

 

MipiRxOutput.jpg

 

thanks again,

david

16 Replies
Xilinx Employee
Xilinx Employee
2,080 Views
Registered: ‎12-02-2009

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Need following info:

1. which version of MIPI CSI-2 RX Subsystem

2. Line rate (if possible attach the xci)

3. Which Vivado

 

 

2,077 Views
Registered: ‎06-13-2018

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

1) 3.0

2) 1500 Mbps

3) 2018.2

 

I have the xci file but I cannot attach it for some reason. It keeps giving me the following error:

 

0 Kudos
Moderator
Moderator
2,066 Views
Registered: ‎11-09-2015

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hi dcoburn@watchguardvideo.com,

 

To share the xci file, could you try to zip it?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
2,061 Views
Registered: ‎06-13-2018

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hello Florent,

 

I'll give it a try...  File included.

 

thanks,

david

Xilinx Employee
Xilinx Employee
1,954 Views
Registered: ‎03-30-2016

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hello dcoburn@watchguardvideo.com

 

From your XCI, I can see that you are using xczu3eg-sfvc784-2 device. (BANK65)

 

Questions for you.

1. Did you connect VRP pin of bank 65 to GND via 240 ohm resistor ?

    If no, please use the following command as a work-around.

set_property DCI_CASCADE .......

    -- Please see the following AR

       https://www.xilinx.com/support/answers/67565.html

 

2. Are you implementing multiple MIPI IP on the same bank (Bank 65) ??

    -- If yes, you should see the following AR (https://www.xilinx.com/support/answers/71374.html)

        It mentioned that if multiple MIPI IPs are placed in the same bank, they need to be reset at the same time.

      

Best regards

Leo

1,938 Views
Registered: ‎06-13-2018

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hi Leo,

 

1) Yes, pin W9 "IO_T0U_N12_VRP_65" is connected to Gnd via 240ohms.

 

2) I'm not sure if this really applies to your question but "yes, I am also implementing a 4 lane CSI-2 transmitter".  I will be placing some logic between the two IP blocks but for now I am simply rearranging the data and passing it through.  As far as resets I have the following inputs all tied together.

Rx - lite_aresetn, video_aresetn

Tx - s_axis_aresetn

 

I have the system_rst_n (of the Tx module) tied to the system_rst_out (of the Rx module).

 

thanks,

david

Xilinx Employee
Xilinx Employee
1,926 Views
Registered: ‎03-30-2016

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hello dcoburn@watchguardvideo.com

 

1) This is good.

 

2) There is no guideline in PG202/PG232/PG260 to connect RX(Master) to TX(Slave).
    I don't think this is possible. (Let me confirm with our MIPI developer team )

   

Question/request for you.

3) Could you please share your RX-->TX clock connectivity ?

 

4) Could you please confirm both INIT_DONE of your  TX & RX IP asserted ?

    ( even if you are not evaluating MIPI TX at this time. I am expecting both IP INIT_DONE asserted )

 

5) Could you please modify TX shared logic setting ?

    From: Include Shared Logic in example design

    To:Include Shared logic in core

 

Best regards

Leo

0 Kudos
1,909 Views
Registered: ‎06-13-2018

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hi Leo,

 

3) RX --> TX clock connectivity

   a) Both modules have dphy_clk_200M from the same PLL output set to 200Mhz.

   b) I initially had the lite_aclk (RX), video_aclk (RX), & s_axis_aclk (TX) all tied to 150Mhz coming from the same PLL.  I have since changed this value to 180Mhz based on the following equation for video_aclk:

   video_aclk (Mhz) = Line rate (Mbps) * Data_Lanes / 8 / 4.

 

4) I will need to implement the JTAG to AXI IP block to do this but I will take a look at it.

 

5) Ok...  done.  I have not compiled it yet.  My compiles take considerably more time at the new video_aclk rate of 180Mhz.

 

david

Xilinx Employee
Xilinx Employee
1,889 Views
Registered: ‎03-30-2016

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hello dcoburn@watchguardvideo.com

Hello @dhill972, @dhill972

 

3) RX --> TX clock connectivity
a) Both modules have dphy_clk_200M from the same PLL output set to 200Mhz.
b) I initially had the lite_aclk (RX), video_aclk (RX), & s_axis_aclk (TX) all tied to 150Mhz coming from the same PLL.  I have since changed this value to 180Mhz based on the following equation for video_aclk:

video_aclk (Mhz) = Line rate (Mbps) * Data_Lanes / 8 / 4.

 
Actually you should use 187.5MHz instead of 180MHz   ( Calculation : video_aclk = 1500 x 4 / 32 == 187.5 MHz )

-- Depends on your actual data-rate and buffer depth, you may not have any problem using 180MHz.


-- BTW, let find the root-cause if this issue first.

   Later, You will also need to check whether s_axis_aclk frequency is okay or not (Please check PG260 Chapter 3 "Clocking section")

 

>4) I will need to implement the JTAG to AXI IP block to do this but I will take a look at it.

Thank you very much. This information is important.

(a)For MIPI D-PHY IP : Please check register address (0x18) bit[3]. Please confirm whether INIT_DONE is “1”
(b)For MIPI CSI-2 RX IP : You can check for Register (0x00) bit[2].  Please confirm whether Controller Ready is “1”
(c)For MIPI CSI-2 TX IP : Same as (b) above.

 

> 5) Ok...  done.  I have not compiled it yet.  My compiles take considerably more time at the new video_aclk rate of 180Mhz.

 

Affirmative. Please update when you have progress on timing.
## You are using MPSoC US+ speed grade:-2.
      I do not expect any difficulty on timing closure.

 

Thanks & regards
Leo

1,822 Views
Registered: ‎06-13-2018

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Leo,

 

I discovered yesterday afternoon that although my MIPI data is present I am not getting the associated MIPI clock from my SERDES.  Obviously that would cause all kinds of problems, so for now, let me figure out what is happening with the SERDES CSI-2 clock output and if I am still not getting data out of the IP block I will post again.  If it fixes the termination issue and gets data out of the IP block I will repost and mark as resolved.

 

thanks,

david

Xilinx Employee
Xilinx Employee
1,803 Views
Registered: ‎03-30-2016

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hello David dcoburn@watchguardvideo.com

Hello @dhill972, @dhill972

 

1. Thanks for sharing your status.

    Please fix your SERDES device setting so MIPI IP can receive clock signal correctly.

2. Regarding INIT_DONE.

    It seems that your D-PHY RX INIT_DONE is low.

   

    -- If MIPI CSI-2 RX clock/data signal is connected,

        and initialization is done correctly, INIT_DONE should be "1"

    -- If you still see INIT_DONE=0

        Please share your MIPI data/clock lane during initialization.

    -- Please note that your SERDES device (MIPI TX) should output LP-11 condition,

        before you start RX IP initialization.

        LP-11 must long enough ( longer than INIT_VAL register setting) to make initialization process succesfull.

 

Since, David Hill has opened SR for this topic, we can continue our discussion on the email if you wish.

 

Thanks & regards

Leo

XF_DAVID_DPHY_INIT_VAL_REG.png
0 Kudos
1,787 Views
Registered: ‎06-13-2018

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Leo,

 

In regard to your comment

 

"Please note that your SERDES device (MIPI TX) should output LP-11 condition, before you start RX IP initialization.  LP-11 must long enough ( longer than INIT_VAL register setting) to make initialization process succesfull."

 

Does this mean that the incoming clock "cannot" be in continuous clock mode?  Currently I have no good clock but I also have it setup as a continuous clock that never goes into the LP-11 mode.  Will this work?  The data lanes do move in and out of the Low Power mode at the ends of their long packet transmits.

 

david

0 Kudos
Xilinx Employee
Xilinx Employee
1,776 Views
Registered: ‎03-30-2016

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hello David dcoburn@watchguardvideo.com

 

Does this mean that the incoming clock "cannot" be in continuous clock mode? 

Currently I have no good clock but I also have it setup as a continuous clock that never goes into the LP-11 mode.  Will this work? 

 

No, it will not work.

Xilinx MIPI CSI-2 RX IP do support both continuous & non-continuous clock mode.

MIPI D-PHY spec defined that at least 100us of LP-11 state is required during during initialization period. (defined as TINIT in Global Operation Timing parameters table).

MIPI D-PHY IP will not be able to complete initialization process without LP-11 states,

 

The data lanes do move in and out of the Low Power mode at the ends of their long packet transmits.

 

Okay.

But please not that data lanes also required LP-11 state at initialization stage.

 

Thanks & regards

Leo

 

0 Kudos
Xilinx Employee
Xilinx Employee
1,774 Views
Registered: ‎03-30-2016

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution
 
XF_MIPI_INIT.jpg
0 Kudos
2,128 Views
Registered: ‎06-13-2018

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hi Leo,

 

I said I would get back with you once I got my SERDES CSI-2 clock going and this final post in in regard to that.  I was able to get the clock going and the signal levels all straightened out and that allowed the IP block to get initialized and I was able to see that it was getting data using the "Jtag to Axi" IP block.  I wasn't getting anything out of the data port initially but I realized that the VFB block was rejecting my packets for various reasons.  I removed that I was able to see data.  I still have some work to do in regard to cleaning the stream up but things seems to be working at this point.

 

MipiRxOutput.jpg

 

thanks again,

david

Xilinx Employee
Xilinx Employee
1,706 Views
Registered: ‎03-30-2016

Re: ZU3EG - MIPI CSI-2 RX Subsystem problems..

Jump to solution

Hello David dcoburn@watchguardvideo.com

 

Great to hear that from you !! Thanks for the update.

Please create a new thread if you need further assistance.

 

Thanks
Leo

0 Kudos