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Contributor
Contributor
1,739 Views
Registered: ‎07-24-2018

Zynq 7000 Video Pipeline Issue - No Output on HDMI

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I am attempting to modify a Zynq 7000 video pipeline project originally targeting the Zybo development board and doing a HDMI in to VGA out passthrough to work on the Pynq board (I'm using the Arty Z7-20 board file) to do a HDMI in to HDMI out pipeline.  The original Digilent project guide is here: see page 16 - 5 Task Two.

 

I initially had issues with clock regions but was able to overcome that with help from a different post here: https://forums.xilinx.com/t5/Implementation/Vivado-2016-1-Implementation-Error/m-p/894471#M22592

 

However, now this design that validates, synthesizes and builds a bitstream seems to never send a signal to the HDMI monitor.  This is a monitor I've used for other Pynq projects using the HDMI out (which I double checked were still working).  My guess is that I've either miss configured something in the clocking wizard or my constraints file.  I'll post the block design, clocking wizard and constraints hoping someone can catch some silly error I'm making.

 

clock_wizard_settings.jpg

 

pynq_hdmi_in_out_architecture.jpg

 

## HDMI RX Signals
set_property -dict {PACKAGE_PIN P19 IOSTANDARD TMDS_33} [get_ports hdmi_in_clk_n]
set_property -dict {PACKAGE_PIN N18 IOSTANDARD TMDS_33} [get_ports hdmi_in_clk_p]
set_property -dict {PACKAGE_PIN W20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_n[0]}]
set_property -dict {PACKAGE_PIN V20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_p[0]}]
set_property -dict {PACKAGE_PIN U20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_n[1]}]
set_property -dict {PACKAGE_PIN T20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_p[1]}]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_n[2]}]
set_property -dict {PACKAGE_PIN N20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_p[2]}]
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports hdmi_in_ddc_scl_io]
set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports hdmi_in_ddc_sda_io]

## HDMI TX Signals
set_property -dict {PACKAGE_PIN L17 IOSTANDARD TMDS_33} [get_ports hdmi_out_clk_n]
set_property -dict {PACKAGE_PIN L16 IOSTANDARD TMDS_33} [get_ports hdmi_out_clk_p]
set_property -dict {PACKAGE_PIN K18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_n[0]}]
set_property -dict {PACKAGE_PIN K17 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_p[0]}]
set_property -dict {PACKAGE_PIN J19 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_n[1]}]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_p[1]}]
set_property -dict {PACKAGE_PIN H18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_n[2]}]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_data_p[2]}]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports hdmi_hpd]


set_property LOC MMCME2_ADV_X1Y2 [get_cells design_1_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenMMCM.DVI_ClkGenerator]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0]
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Scholar watari
Scholar
1,385 Views
Registered: ‎06-16-2013

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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Hi @dcc3

 

Here is an additional information from me.

Would you make sure it ?

 

---

Can you measure or estimate acctual clock frequency at clk_out1 on clk_wiz_0 ?

 

If this frequency is very different between ideal clock frequency and accutual clock frequency, any monitor can not show video data.

 

FYI

1920x1080@60Hz/color depth=8bit => 148.5[MHz]

 

Best regards,

 

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13 Replies
Scholar watari
Scholar
1,696 Views
Registered: ‎06-16-2013

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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Hi @dcc3

 

I ask you the following question to resolve this issue.

Would you tell me them ?

 

1. What resolution do you define in VTC ?

2. What kind of resolutions do you input to Z7-20 ?

3. What kind of HDMI monitor do you use ?

 

Best regards,

Contributor
Contributor
1,684 Views
Registered: ‎07-24-2018

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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@watari

 

Thanks for the reply!

 

1. I define the resolution in the VTC as 1080p. (the same as in the DVI2RGB)

2. The input I've been using is HDMI output from my laptop who's resolution is set to 1080p.

3. The monitor I'm using is a LG 24MK430H-B.

 

I'm using straight HDMI cables with no DVI converters.  This sink and source worked with a different Z7-20 (Pynq board) project as well using HDMI in/out.

 

 

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Moderator
Moderator
1,678 Views
Registered: ‎11-09-2015

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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Hi @dcc3,

 

  • Are you sure about your sys_clk frequency?
  • You might want to check the locked and underflow signals from the AXI4S to video start debugging.
  • You might want to add an ILA to see which part is not ready to send or accept data
  • You might want ot check the status bus from the AXI4S to Video Out for some debbuging information (see my Xilinx Video Series 8 to understand why).

Hope that helps,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Scholar watari
Scholar
1,665 Views
Registered: ‎06-16-2013

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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Hi @dcc3

 

I suspect the following.

Would you tell me your answer ?

 

- Do you use TMDS_33 IO ?

- Do you implement external pull-up resistance (50ohm) to 3.3V ?

 

Best regards,

 

Contributor
Contributor
1,645 Views
Registered: ‎07-24-2018

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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@watari

 

1. Yes, I'm using the TMDS_33 IO standard in my constraints file for the HDMI in and out pins.

2. I'm using a constant block with '1' on the hdmi out hpd pin - if that's what you're asking.

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Contributor
Contributor
1,639 Views
Registered: ‎07-24-2018

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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@florentw

 

I've tried the system with both a 100 MHz and 200 MHz signal (based on suggestions I've read elsewhere).

 

Thank you for the link to the video series - looks like extremely informative reading.  I wish I would have found your series weeks ago! I've been pulling together information from so many different sources I'm not sure what I'm missing from my toolset.

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Moderator
Moderator
1,635 Views
Registered: ‎11-09-2015

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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Hi @dcc3,

 

You might want to read the user guide for the pynq. The clock is not 100MHz or 200MHz.

 

This might be a good reason why you project is not working. Always start by reading the doc


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar watari
Scholar
1,570 Views
Registered: ‎06-16-2013

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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Hi @dcc3

 

> 2. I'm using a constant block with '1' on the hdmi out hpd pin - if that's what you're asking.

 

OK.

I have another question.

 

How do you detect your HDMI source device without HPD ?

Generally, HPD (Hot Plug Detect) signal is used to detect connection by changing signal level from low to high. (It inclused some low term.)

In your case, some HDMI source device can output video signal. However, other can not output it.

 

Would you make sure and consider it ?

 

If you have any idea, would you show me HDMI source device name and so on ?

 

Best regards,

Moderator
Moderator
1,532 Views
Registered: ‎11-09-2015

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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HI @dcc3,

 

Do you have any updates on this? We you able to have your project working?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
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Registered: ‎07-24-2018

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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@watari

 @florentw

Yes, my design currently only has a hpd signal (using a constant block driving a high value) for the hdmi out going to a monitor (Dell monitor).  

 

So, I'm guessing I need a hpd signal for the hdmi input (coming from the hdmi port from my laptop). With the following constraint:

 

set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports hdmi_rx_hpd] 

 

Also, I'm capturing signals from the hdmi inputs for ddc_scl and ddc_sda but not for the hdmi output.  Is this something I need to correct?

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Scholar watari
Scholar
1,386 Views
Registered: ‎06-16-2013

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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Hi @dcc3

 

Here is an additional information from me.

Would you make sure it ?

 

---

Can you measure or estimate acctual clock frequency at clk_out1 on clk_wiz_0 ?

 

If this frequency is very different between ideal clock frequency and accutual clock frequency, any monitor can not show video data.

 

FYI

1920x1080@60Hz/color depth=8bit => 148.5[MHz]

 

Best regards,

 

0 Kudos
Moderator
Moderator
1,379 Views
Registered: ‎11-09-2015

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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HI @dcc3,

 

Did you changed the frequency of your board (input) clock in your vivado design? As mentioned previously, it was incorrect according to the pynq documentation

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
1,333 Views
Registered: ‎11-09-2015

Re: Zynq 7000 Video Pipeline Issue - No Output on HDMI

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HI @dcc3,

 

Do you have any updates on this?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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