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Observer sergio
Observer
543 Views
Registered: ‎01-29-2019

Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hello,

I have downloaded the example zip file with the entire project from the following link:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/25329832/Zynq+UltraScale+MPSoC+VCU+TRD+2018.3#ZynqUltraScale+MPSoCVCUTRD2018.3-4.1DownloadtheTRD

Afterwards I executed tcl command source vcu_audio_proj.tcl and generate block design project, but when I generate output products, I get following errors:

 

 

[Synth 8-439] module 'vcu_audio_v_frmbuf_wr_0_0_v_frmbuf_wr' not found ["c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_wr_0_0/synth/vcu_audio_v_frmbuf_wr_0_0.v":269]

[Synth 8-6156] failed synthesizing module 'vcu_audio_v_frmbuf_wr_0_0' ["c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_wr_0_0/synth/vcu_audio_v_frmbuf_wr_0_0.v":58]

[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

[Synth 8-439] module 'vcu_audio_v_frmbuf_rd_0_0_v_frmbuf_rd' not found ["c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_rd_0_0/synth/vcu_audio_v_frmbuf_rd_0_0.v":269]

[Synth 8-6156] failed synthesizing module 'vcu_audio_v_frmbuf_rd_0_0' ["c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_rd_0_0/synth/vcu_audio_v_frmbuf_rd_0_0.v":58]

[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

 

 

Some of the warnings I get and they seem to have relationship with previous erros are:

 

[IP_Flow 19-3664] IP 'vcu_audio_v_frmbuf_wr_0_0' generated file not found 'c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_wr_0_0/vcu_audio_v_frmbuf_wr_0_0.dcp'. Please regenerate to continue.

[IP_Flow 19-3664] IP 'vcu_audio_v_frmbuf_wr_0_0' generated file not found 'c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_wr_0_0/vcu_audio_v_frmbuf_wr_0_0_stub.v'. Please regenerate to continue.

[IP_Flow 19-3664] IP 'vcu_audio_v_frmbuf_wr_0_0' generated file not found 'c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_wr_0_0/vcu_audio_v_frmbuf_wr_0_0_stub.vhdl'. Please regenerate to continue.

[IP_Flow 19-3664] IP 'vcu_audio_v_frmbuf_wr_0_0' generated file not found 'c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_wr_0_0/vcu_audio_v_frmbuf_wr_0_0_sim_netlist.v'. Please regenerate to continue.

[IP_Flow 19-3664] IP 'vcu_audio_v_frmbuf_wr_0_0' generated file not found 'c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_wr_0_0/vcu_audio_v_frmbuf_wr_0_0_sim_netlist.vhdl'. Please regenerate to continue.

 

[IP_Flow 19-3664] IP 'vcu_audio_v_frmbuf_rd_0_0' generated file not found 'c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_rd_0_0/vcu_audio_v_frmbuf_rd_0_0.dcp'. Please regenerate to continue.

[IP_Flow 19-3664] IP 'vcu_audio_v_frmbuf_rd_0_0' generated file not found 'c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_rd_0_0/vcu_audio_v_frmbuf_rd_0_0_stub.v'. Please regenerate to continue.

[IP_Flow 19-3664] IP 'vcu_audio_v_frmbuf_rd_0_0' generated file not found 'c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_rd_0_0/vcu_audio_v_frmbuf_rd_0_0_stub.vhdl'. Please regenerate to continue.

[IP_Flow 19-3664] IP 'vcu_audio_v_frmbuf_rd_0_0' generated file not found 'c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_rd_0_0/vcu_audio_v_frmbuf_rd_0_0_sim_netlist.v'. Please regenerate to continue.

[IP_Flow 19-3664] IP 'vcu_audio_v_frmbuf_rd_0_0' generated file not found 'c:/VivadoProjects/edt/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_frmbuf_rd_0_0/vcu_audio_v_frmbuf_rd_0_0_sim_netlist.vhdl'. Please regenerate to continue.

 

There are still about 48 warnings like those ones.

 

Any idea to remove those warnings and fix the errors?

Thank you very much.

I am using Vivado 2018.3 in Windows 8.1

 

 

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14 Replies
Scholar watari
Scholar
497 Views
Registered: ‎06-16-2013

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi @sergio 

 

It is well known issue.

The route cause is the limitation of path length issue.

 

You can choose the solution from the followings.

Would you try it ?

 

1) Change OS from Windows to Linux.

=> Because supported OS of TRD is only Linux.

 

2) Change tcl script file to resolve path length issue.

=> You should change some instance name too short.

 

3) Change the setting of Windows

=> Would you refer my suggestion on the following post ?

https://forums.xilinx.com/t5/General-Technical-Discussion/Windows-path-length-issues-any-plans-to-fix/m-p/928885#M42705

 

Best regards,

Observer sergio
Observer
483 Views
Registered: ‎01-29-2019

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi watari,

thank you very much for your answer.

I think I will change to Linux finally, but I will take a look first if there is a way of changing Windows settings in Windows 8.1 to change path length. 

I will let you know if that (running the example in Linux) worked; I guess it should work fine.

Thank you very much once more.

Sergio.

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Observer sergio
Observer
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Registered: ‎01-29-2019

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi,

I finally changed to Ubuntu 16.04.

I am able to regenerate the block design with no problem. I let synthesis running for 8 hours, but never ends. Actually it seems that it was frozen, so I just stopped synthesis.

I am using an i7 with 8GB RAM with Ubuntu 16.04. What are PC requirements in order to be able to run Synthesis, Implementation and Bitstream generation in a reasonable time; let say 1 hour, more or less.

I guess it is possible to run Synthesis, Implementation and Bitstream generation without any problem from the downlable example "Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio", is not it?

 

At the moment I got no error message, but I got following critical warnings:


[IP_Flow 19-182] Failed to load BOM file '/home/VivadoProjects/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_clk_wiz_0_0/vcu_audio_clk_wiz_0_0.xml'.

[IP_Flow 19-183] Failed to load IP instance 'vcu_audio_clk_wiz_0_0'.

[IP_Flow 19-1835] Failed to recreate IP instance 'vcu_audio_clk_wiz_0_0'. Error reading project file(s).

[IP_Flow 19-182] Failed to load BOM file '/home/VivadoProjects/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_clk_wiz_1_0/vcu_audio_clk_wiz_1_0.xml'.

[IP_Flow 19-183] Failed to load IP instance 'vcu_audio_clk_wiz_1_0'.

[IP_Flow 19-1835] Failed to recreate IP instance 'vcu_audio_clk_wiz_1_0'. Error reading project file(s).


Any idea?

Thank you very much.
Sergio

 

 

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Moderator
Moderator
429 Views
Registered: ‎11-09-2015

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

HI @sergio ,

You should be able to go to the full flow without error.

Can you provide the vivado.log you are getting when building this project?

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer sergio
Observer
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Registered: ‎01-29-2019

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi Florent,

thank you very much for your answer.

I can not find any "vivado.log" file, but I found several "vivado_hls.log" files instead, which I attach. I have added numbers 0, 1, 2, 3 and 4 respectively to "vivado_hls_xxx.log".

They were located in different runs.

I was thinking in switch to version 2018.2 instead of 2018.3 as was proposed in this link:

https://forums.xilinx.com/t5/Design-Entry/Since-version-2018-3-get-quot-CRITICAL-WARNING-IP-Flow-19-183/td-p/921425

Because I am getting exactly CRITICAL WARNINGS like those ones, and once I am able to finish synthesis I got error related to those critical warnings.

CRITICAL WARNINGS:

- [IP_Flow 19-182] Failed to load BOM file '/home/VivadoProjects/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_ibufds_gt_0/vcu_audio_ibufds_gt_0.xml'.

- [IP_Flow 19-183] Failed to load IP instance 'vcu_audio_ibufds_gt_0'.

- [IP_Flow 19-1835] Failed to recreate IP instance 'vcu_audio_ibufds_gt_0'. Error reading project file(s).

ERRORS:

[Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

 

If you think I can provide you with anything else that could be of any help, please let me know.

 

Another issue I am facing is when trying to regenerate an IP Core; in this case I tried with "audio_clock_recovery", I got 484 Message errors when regenerating output products.

 

Thank you very much Florent.

Kind regards,

Sergio

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi @sergio ,

I do not think this is related to the forums topic.

Note: the vivado.log is located where you launch vivado not in the project repo. Just type pwd in the tcl console when you start vivado, this is where the vivado.log is created.

Also, maybe the zip is corrupted. Could you try to download the TRD again?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer sergio
Observer
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Registered: ‎01-29-2019

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi Florent,

 

I have just downloaded a fresh zip file and hopefully I will be able to run Synthesis, Implementation and Bitstream generation, but not too optimistic.

 

I will take a look with this new project about the "vivado.log" file and in case I keep having problems I will upload it. 

 

Thank you very much for your support Florent.

Kind regards,

Sergio

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Observer sergio
Observer
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Registered: ‎01-29-2019

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi Florent,


I downloaded again the zip file and tried to run synthesis but the PC was frozen as last time I tried. I thought maybe it was doing synthesis, but after 20 hours waiting I decided to shut down the PC.

From the first synthesis try, I attach following files:

- vivado_first_try.log: This is actually "vivado.log" file.

- vivado_pid14509.str.txt

After starting up the PC, I have started again Vivado and it was running synthesis (still running) but showing one error this time. For this second try I attach:

- vivado_second_try.log: Current "vivado.log" file.

- vcu_audio_v_hdmi_tx_ss_0_0_synth_1.log: It is the log message copied directly from Vivado's gui.

- bd_c1c0_v_tc_0_clocks.xdc.txt: It is a file I get a warning from. It is actually "bd_c1c0_v_tc_0_clocks.xd"


Do you maybe know why my PC freezes every time I try to synthesize the design first time, i.e. when I download the zip file, regenerate block design and run synthesis?

Why do I get following warning if the file is complaining about is in that place?

WARNING: [Vivado 12-818] No files matched '/home/sferrandiz/VivadoProjects/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_audio/vcu_audio.srcs/sources_1/bd/vcu_audio/ip/vcu_audio_v_hdmi_tx_ss_0_0/bd_0/ip/ip_1/bd_c1c0_v_tc_0_clocks.xdc'

What would you recommend me to do?


Thank you very much.

Kind regards,

Sergio

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Scholar watari
Scholar
353 Views
Registered: ‎06-16-2013

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi @sergio 

 

> tried to run synthesis but the PC was frozen as last time I tried.

 

How many memory size do you prepare in Ubuntu ?

I guess there is 8GB.

If yes, because Ubuntu use larger memory size than ReadHat and CentOS, I suggest you to add more memory.

 

Best regards,

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Observer sergio
Observer
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Registered: ‎01-29-2019

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi watari,

 

thank you very much for your answer. You are right, I have 8 GB memory.

Definitely I will have to add some more memory to my PC.

 

Thanks watari for your suggestion.

Kind regards,

Sergio

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

HI @sergio ,

Did adding more memory helped you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer max_selles
Observer
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Registered: ‎09-06-2018

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi,

I have the same issue but my PC has 128GB of DDR4.

(I'm building a RTL kernel for an Alveo U200 on Ubuntu 18.04)

 

[IP_Flow 19-182] Failed to load BOM file '/home/maip/workspace/fft_hdl/vivado_rtl_kernel/fft_kernel_ex/fft_kernel_ex.srcs/sources_1/bd/fft_kernel_bd/ip/fft_kernel_bd_blk_mem_gen_0_0_2/fft_kernel_bd_blk_mem_gen_0_0.xml'.
[IP_Flow 19-183] Failed to load IP instance 'fft_kernel_bd_blk_mem_gen_0_0'.
[IP_Flow 19-1835] Failed to recreate IP instance 'fft_kernel_bd_blk_mem_gen_0_0'. Error reading project file(s).
[Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

 

Best regards.

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

HI @max_selles ,

This is not the same issue as the project you are running is not the VCU TRD and is not targetting the ZCU106...

Please create a new topic on the forums for your issue.

Thank you for your understanding,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer sergio
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Registered: ‎01-29-2019

Re: Zynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Capture and HDMI Display With Audio

Hi Florent,

 

the issue is not yet solved. At the moment I leave it, but I will continue in the future to try to fix it.

 

Kind regards,

Sergio

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