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Participant brianvg
Participant
238 Views
Registered: ‎11-02-2014

Zynq+UltraScale+MPSoC+VCU+TRD+2018.3

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Hi,

Doing some work to port portions of the subject line TRD to a new hardware platform, and I noticed that some of the frame buffer DMA engines use 32 bit addressing and some use 64 bit addressing. All of the video data path elements only interact with the DDR_LOW regions of the memory, which should only require the first 32 bits of the address map. Is this on purpose, or an oversight? I would think that removing the upper order addressing bits could/should save some resources in the mapped design.

 

Thanks,

 

Brian

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Moderator
Moderator
139 Views
Registered: ‎11-09-2015

Re: Zynq+UltraScale+MPSoC+VCU+TRD+2018.3

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Hello @brianvg 

Do you have any updates on this? Were you able to find an answers?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
172 Views
Registered: ‎11-09-2015

Re: Zynq+UltraScale+MPSoC+VCU+TRD+2018.3

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Hi @brianvg ,

Could you clarify which design of the TRD you are talking about? And also which frame buffer you saw configured for 32-bit addressing?

I checked the full vcu trd design ands all the frame buffers are configured for 64 bit addressing


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
140 Views
Registered: ‎11-09-2015

Re: Zynq+UltraScale+MPSoC+VCU+TRD+2018.3

Jump to solution

Hello @brianvg 

Do you have any updates on this? Were you able to find an answers?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Participant brianvg
Participant
122 Views
Registered: ‎11-02-2014

Re: Zynq+UltraScale+MPSoC+VCU+TRD+2018.3

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Hi Florent,

 

Thanks for getting back to me on this. 

 

I am sorry, I wrote the wrong name in the subject line. I should have said the "zcu106_HDMI_ref" design. I ran this design in windows and I guess that some of the parameters were not set correctly. I think you can mark this as solved.

 

Best Regards,

 

Brian

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