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Visitor des_rolf
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Registered: ‎10-03-2018

Zynq Ultrascale+ ZCU106-vcu-trd-2018-3/pl/vcu_sdirxtx

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Hi

I am trying to synthesis the Xilinx supplied VCU_SDIRXTX example design on the ZCU106 Evaluation Platform in Vivado 2018.3.

Synthesis returns the following errors:

(1) [Synth 8-439] module 'system_basic_v_frmbuf_wr_0_0_v_frmbuf_wr' not found ["c:/projects/TRD_2018_3/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_sdirxtx/vcu_sdirxtx.srcs/sources_1/bd/system_basic/ip/system_basic_v_frmbuf_wr_0_0/synth/system_basic_v_frmbuf_wr_0_0.v":273]

(2) [Synth 8-439] module 'system_basic_v_frmbuf_rd_0_0_v_frmbuf_rd' not found ["c:/projects/TRD_2018_3/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_sdirxtx/vcu_sdirxtx.srcs/sources_1/bd/system_basic/ip/system_basic_v_frmbuf_rd_0_0/synth/system_basic_v_frmbuf_rd_0_0.v":273]

(3) [Synth 8-439] module 'system_basic_v_mix_0_0_v_mix' not found ["c:/projects/TRD_2018_3/rdf0428-zcu106-vcu-trd-2018-3/pl/vcu_sdirxtx/vcu_sdirxtx.srcs/sources_1/bd/system_basic/ip/system_basic_v_mix_0_0/synth/system_basic_v_mix_0_0.v":635]

I can add these as IP, but the supplied source files appear to be incomplete. 

All 3 of these errors relate to HLS components.

I have not modified the example design in anyway, I just want to run synthesis and implementation.

Does anyone know how to overcome this issue please?

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Moderator
Moderator
178 Views
Registered: ‎04-12-2017

Re: Zynq Ultrascale+ ZCU106-vcu-trd-2018-3/pl/vcu_sdirxtx

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Hello @des_rolf 

I consider here that you are working in the Windows 10 OS from the error description you have shared.

The best solution to avoid this HLS issues is to reduce the path length from where you are calling the project tcl file.

I usually follow below steps to open the project from vivado.

1. open cmd prompt tool.

2. Move to path cd C:\trd\pl (here I have renamed the TRD directory with shorter name and moved trd directory to root folder)

3. C:\Xilinx\Vivado\2018.3\settings64.bat

4. vivado -source ./scripts/vcu_sdirxtx_proj.tcl

above steps open the project in the above path from vivado.

The issue you are facing resembles to the following AR

https://www.xilinx.com/support/answers/52787.html

Above steps will surely help you resolve this isse.

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3 Replies
Moderator
Moderator
179 Views
Registered: ‎04-12-2017

Re: Zynq Ultrascale+ ZCU106-vcu-trd-2018-3/pl/vcu_sdirxtx

Jump to solution

Hello @des_rolf 

I consider here that you are working in the Windows 10 OS from the error description you have shared.

The best solution to avoid this HLS issues is to reduce the path length from where you are calling the project tcl file.

I usually follow below steps to open the project from vivado.

1. open cmd prompt tool.

2. Move to path cd C:\trd\pl (here I have renamed the TRD directory with shorter name and moved trd directory to root folder)

3. C:\Xilinx\Vivado\2018.3\settings64.bat

4. vivado -source ./scripts/vcu_sdirxtx_proj.tcl

above steps open the project in the above path from vivado.

The issue you are facing resembles to the following AR

https://www.xilinx.com/support/answers/52787.html

Above steps will surely help you resolve this isse.

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Moderator
Moderator
137 Views
Registered: ‎11-09-2015

Re: Zynq Ultrascale+ ZCU106-vcu-trd-2018-3/pl/vcu_sdirxtx

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Hi @des_rolf ,

Do you have any updates on this? Was @kvasantr's reply enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor des_rolf
Visitor
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Registered: ‎10-03-2018

Re: Zynq Ultrascale+ ZCU106-vcu-trd-2018-3/pl/vcu_sdirxtx

Jump to solution
Hi.
Thanks for your suggestion. I decided to move from Windows to Linux and the TRD worked out of the box.
Thanks.
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