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Contributor
Contributor
534 Views
Registered: ‎09-17-2018

Zynq Ultrascale+: test MIPI CSI-2 RX without camera input

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Hi,

I have a requirement to test the MIPI CSI-2 receiver in Zynq US+ and visualize the video input using display port.

However, we don't have the CSI camera in place currently. So my idea is to use a test pattern generater as the video source and connect it through a CSI TX to the CSI RX. But this design cannot be compiled when I connect the mipi_phy ports of CSI TX and RX together. I guess this could be solved by only using the CSI RX/TX controller sub cores but I have no idea of how to remove the physical layer.

Do you have any suggestion on this?

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Xilinx Employee
Xilinx Employee
498 Views
Registered: ‎03-30-2016

Re: Zynq Ultrascale+: test MIPI CSI-2 RX without camera input

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Hello @xinyiz

1. If you want to test/verify MIPI CSI-2 RX Subsystem IP. Please follow instruction described in PG232 Chapter 5.  
   https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_rx_subsystem/v4_0/pg232-mipi-csi2-rx.pdf

 This is your easiest option.
  You will need to purchase ZCU102 board and LI-IMX274MIPI-FMC Camera though.

2. You may also want to try TRD (Targeted Reference Design) for ZCU102
    https://www.xilinx.com/support/documentation/boards_and_kits/zcu102/2017_2/ug1221-zcu102-base-trd.pdf
    https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/45940846/Zynq+UltraScale+MPSoC+Base+TRD+2018.3

    You will also need to purchase ZCU102 board and LI-IMX274MIPI-FMC Camera though.

 

>this design cannot be compiled when I connect the mipi_phy ports of CSI TX and RX together

Yes. This is an expected behavior.
MIPI D-PHY TX output pins and D-PHY RX input pins shall be assigned on HP I/O bank pins.

>I guess this could be solved by only using the CSI RX/TX controller sub cores but I have no idea of how to remove the physical layer.

Xilinx provides MIPI CSI-2 RX and TX as a subsystem IP. CSI-2 RX/TX Controller only usage is not supported.   
So, You will need a MIPI CSI-2 serial data from external sources to test MIPI CSI-2 RX Subsystem IP.

Thanks & regards
Leo

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2 Replies
Xilinx Employee
Xilinx Employee
499 Views
Registered: ‎03-30-2016

Re: Zynq Ultrascale+: test MIPI CSI-2 RX without camera input

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Hello @xinyiz

1. If you want to test/verify MIPI CSI-2 RX Subsystem IP. Please follow instruction described in PG232 Chapter 5.  
   https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_rx_subsystem/v4_0/pg232-mipi-csi2-rx.pdf

 This is your easiest option.
  You will need to purchase ZCU102 board and LI-IMX274MIPI-FMC Camera though.

2. You may also want to try TRD (Targeted Reference Design) for ZCU102
    https://www.xilinx.com/support/documentation/boards_and_kits/zcu102/2017_2/ug1221-zcu102-base-trd.pdf
    https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/45940846/Zynq+UltraScale+MPSoC+Base+TRD+2018.3

    You will also need to purchase ZCU102 board and LI-IMX274MIPI-FMC Camera though.

 

>this design cannot be compiled when I connect the mipi_phy ports of CSI TX and RX together

Yes. This is an expected behavior.
MIPI D-PHY TX output pins and D-PHY RX input pins shall be assigned on HP I/O bank pins.

>I guess this could be solved by only using the CSI RX/TX controller sub cores but I have no idea of how to remove the physical layer.

Xilinx provides MIPI CSI-2 RX and TX as a subsystem IP. CSI-2 RX/TX Controller only usage is not supported.   
So, You will need a MIPI CSI-2 serial data from external sources to test MIPI CSI-2 RX Subsystem IP.

Thanks & regards
Leo

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Moderator
Moderator
436 Views
Registered: ‎11-09-2015

Re: Zynq Ultrascale+: test MIPI CSI-2 RX without camera input

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Hi @xinyiz,

Do you have any updates on this? Was @karnanl's reply enough for you?

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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