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Observer haidoph
Observer
1,287 Views
Registered: ‎02-24-2014

about displayport ip (7.0) as sink ,The output resolution of the different graphics card

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hello,

    when used to  IMAC/MAC pro ,Edid reads correctly and the graphics card output resolution is correct,Links are usually successful。

    but When I use the graphics card(AMD v3800) of the windows operating system,EDID reads correctly, but the graphics card output pulls down the resolution and only outputs 800x600.Links will not succeed.

 

Is it related to the operating system? Or displayport ip(7.0) needs special configuration?

 

thanks!!!

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1 Solution

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Scholar watari
Scholar
1,555 Views
Registered: ‎06-16-2013

Re: about displayport ip (7.0) as sink ,The output resolution of the different graphics card

Jump to solution

Hi @haidoph

 

As I and @florentw already mentioned before, I strongly suggest to use latest DisplayPort Rx IP even if you use ZC7045 (Zynq 7045).

This Zynq 7045 has like Kintex-325 as FPGA fabric.

Therefore you can refer example design of KC705.

Would you try it ?

 

By the way, I suspect that the route cause is jitter or SI or lane selection algorithm of DP by wrong EDID.

If you are interesting about it, would you make sure them ?

If the route cause seems wrong EDID, would you change maximum vertical frequency from 75Hz to 60Hz in EDID ?

 

[Note]

Jitter : TB-FMCH-DP3.1 has a "DP159RGZ" as retimer. If you don't implement it, it might be occurred jitter issue.

SI : DP has some PCB guideline. If you ignore like it without SI confirmation, it might be occurred SI issue. Or, it it related to an attenuated issue. If yes, you might be modified some compensation parameter and c language source code for equalizer at DP sink or for emphasis at DP source.

lane selection algorithm : Video card's driver should be followed EDID and appropriately output video signal (DP packet) with video timing. However, if video card's driver misunderstand what DP sink want, it might be occurred like this issue.

 

[Information]

As you know, when DP failed link training or something for any reason, DP source device output 800x600@60Hz by RBR for fail-safe on Windows Viasta (or XP) or later.

 

Best regards,

8 Replies
Scholar watari
Scholar
1,256 Views
Registered: ‎06-16-2013

Re: about displayport ip (7.0) as sink ,The output resolution of the different graphics card

Jump to solution

Hi @haidoph

 

Your information is not sufficient to reply your question.

Would you show at least the following information ?

 

- System diagram

- FPGA device

- Target resolution

 

Also, at least, DisplayPort IP v7.0 is discontinued IP. I suggest to use DisplayPort Rx subsystem over ver. 2.0.

 

https://www.xilinx.com/support/documentation/ip_documentation/dp_rx_subsystem/v2_1/pg233-displayport-rx-subsystem.pdf

 

[Your environment (My understanding)]

case a) iMac and Mac Pro -(DP ? Thunderbolt ? or other ?/Protocol = DisplayPort ?)-> FPGA board ?

case b) Windows PC (OS ?) with AMD v3800 (Driver version ?) -(DisplayPort)-> FPGA board ?

 

I can not understand case a) and case b)'s resolution.

 

[My opinion]

In my experience, I guess ADM's video card has a little compatibility problem on your environment.

It is related with ADM's video driver and specific to this IP.

 

Best regards

Observer haidoph
Observer
1,229 Views
Registered: ‎02-24-2014

Re: about displayport ip (7.0) as sink ,The output resolution of the different graphics card

Jump to solution

hi,@watari

    

- System diagram

          DP source--> DP sink (dp159 )-->displayport ip 7.0(FPGA)

- FPGA device

          ZYNQ7045

- Target resolution

         1920x1080

 

[Your environment (My understanding)]

case a) iMac and Mac Pro -(DP ? Thunderbolt ? or other ?/Protocol = DisplayPort ?)-> FPGA board ?

           yes, iMAC/Mac pro ( Thunderbolt  or type c = displayport) -->  DP159 -->FPGA 

           EDID reads correctly and the link is successful

           324319759931323303.jpg

case b) Windows PC (OS ?) with AMD v3800 (Driver version ?) -(DisplayPort)-> FPGA board ?

        yes , AMD V3800  tried different version drivers  ,EDID reads correctly , But the resolution is limited to 800x600.

        Link is unsuccessful。Similar situation occurs with the INTEL integrated graphics card 4000series

       Is my displayport IP setting incorrect?How should I find the problem?

       Looked at the xilinx demo XAPP1271/XAPP1178, AMD V3800 is supported

      thanks!!!

       388813406164232352.jpg

   

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Moderator
Moderator
1,220 Views
Registered: ‎11-09-2015

Re: about displayport ip (7.0) as sink ,The output resolution of the different graphics card

Jump to solution

Hi @haidoph,

 

I am surprised to see that the same of the monitor is XILINX HDMI...

 

Anyway, as suggested by @watari, you should use the latest driver for the GPU and use the latest example design for Displayport. Refer to chapter 5 of pg233 to know how to generate the example design. Also make sure to use the latest version of Vivado.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer haidoph
Observer
1,218 Views
Registered: ‎02-24-2014

Re: about displayport ip (7.0) as sink ,The output resolution of the different graphics card

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hi,@

     haha,EDID is copied from XAPP1271,Demo is already running ok(used Inrevium Kintex-7 FPGA ACDC1.0 base board (TB-7K-325T-IMG) +  TB-FMCH-DP3.1     )。But use my board,The above problem will occur。I don't know how to solve the problem now

 

 

   thanks!!!

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Moderator
Moderator
1,215 Views
Registered: ‎11-09-2015

Re: about displayport ip (7.0) as sink ,The output resolution of the different graphics card

Jump to solution

Hi @haidoph,

 

Again, use the example design from vivado.

There was some updates to the application (and to the driver moving to 2018.1). It might help.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer haidoph
Observer
1,211 Views
Registered: ‎02-24-2014

Re: about displayport ip (7.0) as sink ,The output resolution of the different graphics card

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hi,@

    My platform is zynq7045,Demo cannot be used directly。I refer to the demo to debug.

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Scholar watari
Scholar
1,556 Views
Registered: ‎06-16-2013

Re: about displayport ip (7.0) as sink ,The output resolution of the different graphics card

Jump to solution

Hi @haidoph

 

As I and @florentw already mentioned before, I strongly suggest to use latest DisplayPort Rx IP even if you use ZC7045 (Zynq 7045).

This Zynq 7045 has like Kintex-325 as FPGA fabric.

Therefore you can refer example design of KC705.

Would you try it ?

 

By the way, I suspect that the route cause is jitter or SI or lane selection algorithm of DP by wrong EDID.

If you are interesting about it, would you make sure them ?

If the route cause seems wrong EDID, would you change maximum vertical frequency from 75Hz to 60Hz in EDID ?

 

[Note]

Jitter : TB-FMCH-DP3.1 has a "DP159RGZ" as retimer. If you don't implement it, it might be occurred jitter issue.

SI : DP has some PCB guideline. If you ignore like it without SI confirmation, it might be occurred SI issue. Or, it it related to an attenuated issue. If yes, you might be modified some compensation parameter and c language source code for equalizer at DP sink or for emphasis at DP source.

lane selection algorithm : Video card's driver should be followed EDID and appropriately output video signal (DP packet) with video timing. However, if video card's driver misunderstand what DP sink want, it might be occurred like this issue.

 

[Information]

As you know, when DP failed link training or something for any reason, DP source device output 800x600@60Hz by RBR for fail-safe on Windows Viasta (or XP) or later.

 

Best regards,

Moderator
Moderator
1,089 Views
Registered: ‎11-09-2015

Re: about displayport ip (7.0) as sink ,The output resolution of the different graphics card

Jump to solution

Hi @haidoph,

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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