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Participant p.nejad
Participant
742 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hello gentelmen,

I do have video out in slave mode with vtg_ce connected to VTC. 

I looked at eol as watari suggested and confirmed that eol happens at the end of every line with blanking not just the active video. I don't know why this is happening.  

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Scholar watari
Scholar
708 Views
Registered: ‎06-16-2013

Re: axi4s_to_video_out won't lock

Hi @p.nejad

 

I'm not sure. But I guess your setting on vtc by software or the behavior of AFIFO are wrong.

 

For example, if you set wrong horizontal active width on some IP by software, these IPs behave to output wrong eol.

Because of eol signal is generally generated by horizontal active width.

 

The best way to resolve this issue is to set correct parameters on v_tc by software (Plan A) or to generate correct HSYNC/VSYNC/Active data/HBLANK/VBLANK into video-in_axi4s. (Plan B)

 

[Plan A]

I think that it's reasonable way. But it is little difficult to set correct parameter on v_tc.

 

[Plan B]

I'm worried about backpressure capability issue on AFIFO. It's same opinion as @bwiec.

If you can fix this issue, it's very reasonable way for you.

 

Best regards,

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Moderator
Moderator
669 Views
Registered: ‎11-09-2015

Re: axi4s_to_video_out won't lock

Hi @p.nejad,

 

Any updates on this?

 

If everything is clear for you, please kindly close the topic by marking a reply as accepted solution.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Participant p.nejad
Participant
655 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hello,
Thanks for following up!!
I'm still working on it , nothing has changed yet.
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