UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer el3ctrician
Observer
516 Views
Registered: ‎12-04-2018

custom IP causing problems with AxiStream to Video out v4.0

Jump to solution

Hello,

I am trying to create an IP core that acts on a video stream, one of the functionalities of the IP is to simply buffer the first line and then start transmitting the frame after the first line is buffered (kinda of a pass through) it when it's completed. My core have an AXIS_S and AXIS_M to receive and send the video. I created a test using TPG and JTAG to AXI to test the IP and i notice some wired stuff.

BD.PNGBD

If I connect the TPG output to the  axi to video out directly i got the video out and everything is working as expected, when i add my core the stream to video out core won't lock and would rise an underflow signal. Both my core and the TPG are running at the same CLK and produce the same clock.

underflow.PNGUNDERFLOW

i just notice some difference on how i handle the signals of SOF and EOL (TUSER and TLAST) in respect to the core.

i attach also some screenshots from the ILA debugger.

core_TLAST.PNGcore TLASTcore_TUSER.PNGCore TUSERTPG.PNGTPG TUSERTPG_TLAST.PNGTPG TLAST

 

The output stage of my core is made using a FWFT FIFO with VALID and EMPTY signal and is mapped to the AXIS_M in the following way :

 

m_axis_out_tvalid <= fifo_valid;
m_axis_out_tdata <= fifo_dout(23 downto  0);
m_axis_out_tstrb <= fifo_dout(26 downto 24);
m_axis_out_tkeep <= fifo_dout(29 downto 27);
m_axis_out_tlast <= fifo_dout(30);
m_axis_out_tuser(0) <= fifo_dout(31) ; 
fifo_rden <= m_axis_out_tready and not fifo_empty;

i know that tstrb and tkeep are not used but i use them to provide uniformity to previous designed cores. As of my understanding AXI Strem carries only the active video strem with no blanks. I think my output is AXI compliant but i can't understand why it dose not work ?

i came across this link ( https://www.xilinx.com/support/answers/61430.html ) i which for an older version it was suggested to add blank signals but then again i had a look at the( https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf ) just to found out that the AXI dose not carry blank informations.

I am really confused with this informations so my questions are :

1. Is my implementation of the AXI Stream Master is AXI Compliant ?

2. Should I add non valid data in the stream ?

3. Would this be the issue with my video not being displayed correctly ?

4. What other problems would be there (i checked video dimension at the output of the core and seems right) ?

 

NB: The design is made on Vivado 2016.2

 

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
430 Views
Registered: ‎11-09-2015

Re: custom IP causing problems with AxiStream to Video out v4.0

Jump to solution

HI @el3ctrician,

It seems that your block is introducing some blanking between the frames. I am not sure the TPG does that. Or at least the time between frames seems smaller. The AXI4S to video out is using that blanking time to fill its internal FIFO to have enough data.

It might be that slight difference which is causing the issue. Maybe you can solve this by increasing the frequency of the TPG + you custom IP and use a separated video clock (this means 2 clocks connected on the AXI4S to video out - the AXI4S clock + the video clock)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
6 Replies
Moderator
Moderator
453 Views
Registered: ‎11-09-2015

Re: custom IP causing problems with AxiStream to Video out v4.0

Jump to solution

Hi @el3ctrician,

Do you get the underflow signal for each frame. Sometimes it can happen at the beginning but this is not the reason why no video is displayed.

You might want to have a look at my Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP, it gives some tips on debugging when you are not getting the expected output from the AXI4-Stream to Video Out.

Hope that helps,

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Observer el3ctrician
Observer
446 Views
Registered: ‎12-04-2018

Re: custom IP causing problems with AxiStream to Video out v4.0

Jump to solution

Hello @florentw,

Thanks for your answer. As you can see from the attached screen shot the underflow is going up after each frame. I also tried to look at the status output as mentioned from the link you sent to me but i think that the core is in a wired state. More Debug.pngmore Debugging

as you can see a lot of signals are on and i tried to make sense of the data in this way :

  •  The core is idle which could be fine cause it is not getting locked.
  • bit [1] indicates "Course Align, Wait for VTG SOF" but the SOF is correctly transmitted over the AXI Stream ??
  • bit [2] indicates "Course Align, Wait for FIFO SOF" which is fine since the core did not detect the SOF over the AXI in the first place.
  • bits [3] and [4] should refer if the EOL is Leading or Lagging but both are high ?!

The more i debug the more i get confused by this wired issue. The fact that simply removing my custom everything works back. I also tried to add blanks ( keeping TVALID low and  TLAST high at the end of each line ) but no sucess. Data dimensions are identical to the one from the TPG my core introduces only 1 line of latency at the first frame but the pixel rate is identical to the TPG.

0 Kudos
Moderator
Moderator
431 Views
Registered: ‎11-09-2015

Re: custom IP causing problems with AxiStream to Video out v4.0

Jump to solution

HI @el3ctrician,

It seems that your block is introducing some blanking between the frames. I am not sure the TPG does that. Or at least the time between frames seems smaller. The AXI4S to video out is using that blanking time to fill its internal FIFO to have enough data.

It might be that slight difference which is causing the issue. Maybe you can solve this by increasing the frequency of the TPG + you custom IP and use a separated video clock (this means 2 clocks connected on the AXI4S to video out - the AXI4S clock + the video clock)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Observer el3ctrician
Observer
344 Views
Registered: ‎12-04-2018

Re: custom IP causing problems with AxiStream to Video out v4.0

Jump to solution

Hello,
thanks for the tip. I got some wired behavior of my core at higher frequency so I am debugging the issue now. I will update the topic as soon as i have some new progress.

Thanks

0 Kudos
Observer el3ctrician
Observer
322 Views
Registered: ‎12-04-2018

Re: custom IP causing problems with AxiStream to Video out v4.0

Jump to solution
Thanks @florentw, after trying with your tip i found out that my core did not manage well the FIFO overflow, am talking about my internal FIFO that i used as output device. After managing the overflow situation, that was not visible in the lower frequency everything worked as expected even on the lower frequency.
Thanks for the tip i suggest anyone facing a similar issue to try the mentioned method here.
Moderator
Moderator
317 Views
Registered: ‎11-09-2015

Re: custom IP causing problems with AxiStream to Video out v4.0

Jump to solution

Hi @el3ctrician,

Good to know that you solved your issue and thank you for sharing your solution ;)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos