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Observer parithyila
Observer
1,114 Views
Registered: ‎04-09-2019

display port and vedio phy controller

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Hi 

I am working with dispaly port and video phy contrller, i have attached the integrated block diagram pls have a look on it.

when i am reading the PLL Lock Status (PLS) Register (0x0018) of vedio phy controller all the values in the register are 0, from that i understood that my qpll is not locked.

below is the sequence of writing data to vedio phy controller

1.write PLL Reset Register (PR) (0x0014)   seting all the bits 1

2.write Reference Clock Selection (RCS) Register (0x0010)  =C000031  

3. write PLL Reset Register (PR) (0x0014)   seting all the bits 1

4.reading PLL Lock Status (PLS) Register (0x0018)

if i read the PHY Configuration Status from sp 0x280 i am geting the value 6c is this correct.

I am using 135 Mhz clock for all my design, why my qpll status is alway 0 ,

i am using vivado 2016.4

pls verify the below attached block diagrm . let me know  why  qpll status is alway 0

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Moderator
Moderator
852 Views
Registered: ‎10-04-2017

Re: display port and vedio phy controller

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As Watari mentioned jitter needs to be considered for this clock as it is a GT clock. I do not suggest using an internal clock.

GT clock requirements are listed in each of the DC and AC Switching Characteristics guides. 

 

As an example here is the table for the Kintex Ultrascale DS893. Use the Phase Noise Mask to select a clock chip. Vendors usually have phase noise listed in their documentation.

 

2019-08-30 08_36_53-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

 

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Xilinx Video Design Hub
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Moderator
Moderator
1,028 Views
Registered: ‎10-04-2017

Re: display port and vedio phy controller

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Hi @parithyila,

 

Directly programming the registers is not supported, please use the drivers as the process to initializing can be complicated and this already written and tested for you by our drivers. Is there a reason that you are using 2016.4? Check the ARs below for all of the improvements and bug fixes since 2016.4. Also there is an example design available starting in 2017.3.

RX:

http://www.xilinx.com/support/answers/65447.htm

 

TX:

http://www.xilinx.com/support/answers/59384.htm

 

PHY:

http://www.xilinx.com/support/answers/57842.htm

 

My suggestion is to upgrade to Vivado 2017.3 or newer and use the example design as a reference and as a tool to test your hardware (if on custom hardware).

 

 

 

 

 

 

 

 

 

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Observer parithyila
Observer
977 Views
Registered: ‎04-09-2019

Re: display port and vedio phy controller

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Hi samk,

thanks for replying,

I am not clear about driver you have mentioned . are your saying about  microblaze ? 

Right now i am using Axi master as a driver  to drive the register values . Do i need to drive the value through microblaze?

 

regards

ilam

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Moderator
Moderator
956 Views
Registered: ‎10-04-2017

Re: display port and vedio phy controller

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Hi @parithyila,

 

Yes, a processor is required for the Video PHY controller. Either an ARM (Zynq) or MicroBlaze.

Take a look at one of the example designs and I believe this will answer your questions.

 

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Observer parithyila
Observer
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Registered: ‎04-09-2019

Re: display port and vedio phy controller

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Hi samk,

Thanks for your reply i will come back if there is any need

 

 

regads

ilam

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Observer parithyila
Observer
926 Views
Registered: ‎04-09-2019

Re: display port and vedio phy controller

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Hi samk,

can we generate 135Mhz internally from FPGA   or we need to use external clock as a reference clock for viedo phy controller,

right now i am generating internally.

 

regards

ilam

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Scholar watari
Scholar
889 Views
Registered: ‎06-16-2013

Re: display port and vedio phy controller

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Hi @parithyila 

 

You should consider input clock jitter for DP IP.

So, I suggest you to use external clock device which has low clock jitter as reference clock.

 

Best regards,

Moderator
Moderator
853 Views
Registered: ‎10-04-2017

Re: display port and vedio phy controller

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As Watari mentioned jitter needs to be considered for this clock as it is a GT clock. I do not suggest using an internal clock.

GT clock requirements are listed in each of the DC and AC Switching Characteristics guides. 

 

As an example here is the table for the Kintex Ultrascale DS893. Use the Phase Noise Mask to select a clock chip. Vendors usually have phase noise listed in their documentation.

 

2019-08-30 08_36_53-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Moderator
Moderator
643 Views
Registered: ‎11-21-2018

Re: display port and vedio phy controller

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Hi @parithyila 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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