08-22-2019 12:30 AM
i am doing Video Displayport 1.4 rx subsytem Example design. But by default it have zcu102 evalution board (xczu9eg-ffvb1156-2-e).But i want to change part number with xczu6eg-ffvc900-1-e. So i want to change constraints.where can i get constrains of xczu6eg-ffvc-900-1-e part. can anyone help me please.
08-22-2019 10:46 PM - edited 08-22-2019 10:47 PM
Hello email@example.com ,
The Zynq UltraScale+ MPSoC Package all Device Pinout Files are available in the below link,
The part number XCZU6eg-ffvc900-1-e, pin out text file is addressed in the below link
Kindly let me know, if you face any problem, while using the above links.
08-23-2019 12:48 AM
DisplayPort1.4 RX example designs are created for VCU118, KC705 and ZCU102 boards only. If you want to port this example design to your custom Xilinx FPGA board, then you need to understand default example design pinout connections and then remap this connections according to your FPGA board.
08-23-2019 03:07 AM
i changed the pinouts according to xczu6eg-ffvb900-1-e. bu.t i got the errors in placement.see the below attachment.
08-23-2019 03:31 AM
08-29-2019 05:26 AM
08-29-2019 03:37 PM
I guess you might execute Vivado on Windows.
If yes, you are facing file path length issue (instance length issue) like you mentioned before.
So, I suggest you to reduce file path length or change OS from Windows to Linux or modify registory value by regedit and so on or change policy by policy editor.
09-11-2019 03:09 AM
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