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385 Views
Registered: ‎03-10-2019

display port rx subsystem

i am doing Video Displayport 1.4 rx subsytem Example design. But by default it have zcu102 evalution board (xczu9eg-ffvb1156-2-e).But i want to change part number with xczu6eg-ffvc900-1-e. So i want to change constraints.where can i get constrains of xczu6eg-ffvc-900-1-e part. can anyone help me please.

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7 Replies
Xilinx Employee
Xilinx Employee
338 Views
Registered: ‎04-09-2019

Re: display port rx subsystem

Hello sy5809358@gmail.com  ,

The Zynq UltraScale+ MPSoC Package all Device Pinout Files are available in the below link,

https://www.xilinx.com/support/package-pinout-files/zynq-ultrascale-plus-pkgs.html

The part number XCZU6eg-ffvc900-1-e, pin out text file is addressed in the below link

https://www.xilinx.com/support/packagefiles/zuppackages/xczu6egffvc900pkg.txt

Kindly let me know, if you face any problem, while using the above links.

With Regards,

Ashok

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Xilinx Employee
Xilinx Employee
324 Views
Registered: ‎03-07-2018

Re: display port rx subsystem

Hello sy5809358@gmail.com 

DisplayPort1.4 RX example designs are created for VCU118, KC705 and ZCU102 boards only. If you want to port this example design to your custom Xilinx FPGA board, then you need to understand default example design pinout connections and then remap this connections according to your FPGA board.

Regards,
Bhushan

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314 Views
Registered: ‎03-10-2019

Re: display port rx subsystem

i changed the pinouts according to xczu6eg-ffvb900-1-e. bu.t i got the errors in placement.see the below attachment.

1.png
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Xilinx Employee
Xilinx Employee
307 Views
Registered: ‎04-09-2019

Re: display port rx subsystem

Hi sy5809358@gmail.com 

I hope the BUFG's are exceeded in the design with the FPGA what you had selected. Could You Please Confirm this.

With Regards,

Ashok.

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Xilinx Employee
Xilinx Employee
263 Views
Registered: ‎04-09-2019

Re: display port rx subsystem

Hi sy5809358@gmail.com 

May I know the status of this case, If your case was resolved with our inputs, please mark it as accepted solution.

With Regards,

Ashok

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Scholar watari
Scholar
251 Views
Registered: ‎06-16-2013

Re: display port rx subsystem

Hi sy5809358@gmail.com 

 

I guess you might execute Vivado on Windows.

If yes, you are facing file path length issue (instance length issue) like you mentioned before.

So, I suggest you to reduce file path length or change OS from Windows to Linux or modify registory value by regedit and so on or change policy by policy editor.

 

Best regards,

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Moderator
Moderator
182 Views
Registered: ‎11-21-2018

Re: display port rx subsystem

Hi sy5809358@gmail.com 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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