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73 Views
Registered: ‎03-10-2019

displayport_rx_subsystem

i am doing displayport_rx_subsystem..i am implementing block design manually but i didn't get the vid_edid_v1_o.please can any one suggest me how to get that ip.

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Registered: ‎11-09-2015

Re: displayport_rx_subsystem

Hi sy5809358@gmail.com 

The Vid_EDID block ais what we call an helper core. Helper coresare used in the example designs to demonstrate the behaviour of the Displayport core but they are not supported by Xilinx. Users are expected to write their own IPs for this blocs. This is why they are not part of the IP catalog and why there is not documnetation available.

You could potentially start from the example design to do your own project, but keep in mind that this is not fully supported.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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