UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
341 Views
Registered: ‎03-10-2019

displayport tx subsystem

Jump to solution

I am implementing display port tx subsystem on xczu9eg-ffvc900-1-e part.In this design utility buffer is used.in utility buffer i am using cbuf type is IBUFDSGTE.my doudt is how to give differential input to the utility buffer..is it required in displayport tx subsystem or is there alternative to give clock.please help me.

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
301 Views
Registered: ‎03-07-2018

Re: displayport tx subsystem

Jump to solution

Hello sy5809358@gmail.com 

First of all I am not very clear with your requirement.

I believe you are talking about utility buffer used in DisplayPort1.4 TX example design mentioned in Chapter 6 of PG299 (v2.1) as follows:

DP14TXExampleUBUF.jpg

UBUF Parameters.jpg

Above snapshot is for DisplayPort1.4 TX example design based on ZCU102 board.

Clock constarints are mentioned in top_zcu102.xdc as follows:

Clk DP14TX constraints.png

MGTREFCLK0 pin connection on ZCU102 board:

REFCLK0 Connection.jpg

MGTREFCLK1 pin connection on ZCU102 board:

REFCLK1 Connection.jpg

You can check more details in UG1182 (v1.6) and ZCU102 Schematics for this connections.

Please check PG230 (v2.2) DisplayPort Clocking section for detailed understanding.

So, as you are using IBUFDSGTE you need to use differential clock only.

Please provide details of your board (Xilinx or custom board, clock sources available on your board etc..), DisplayPort IP version; if you have any further queries.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------
1 Reply
Xilinx Employee
Xilinx Employee
302 Views
Registered: ‎03-07-2018

Re: displayport tx subsystem

Jump to solution

Hello sy5809358@gmail.com 

First of all I am not very clear with your requirement.

I believe you are talking about utility buffer used in DisplayPort1.4 TX example design mentioned in Chapter 6 of PG299 (v2.1) as follows:

DP14TXExampleUBUF.jpg

UBUF Parameters.jpg

Above snapshot is for DisplayPort1.4 TX example design based on ZCU102 board.

Clock constarints are mentioned in top_zcu102.xdc as follows:

Clk DP14TX constraints.png

MGTREFCLK0 pin connection on ZCU102 board:

REFCLK0 Connection.jpg

MGTREFCLK1 pin connection on ZCU102 board:

REFCLK1 Connection.jpg

You can check more details in UG1182 (v1.6) and ZCU102 Schematics for this connections.

Please check PG230 (v2.2) DisplayPort Clocking section for detailed understanding.

So, as you are using IBUFDSGTE you need to use differential clock only.

Please provide details of your board (Xilinx or custom board, clock sources available on your board etc..), DisplayPort IP version; if you have any further queries.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------