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Contributor
Contributor
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Registered: ‎05-02-2018

dp example av_pat_gen

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Hi @florentw ,

As mentioned in topic

https://forums.xilinx.com/t5/Video/tpg-and-dp1-4-IP-not-generating-image/m-p/1016847#M27362

You discuss about replacing tpg with av_pat_gen.

I still have two questions:

1.Could you tell me where can i find the details for dp input changing corresponding to the lane uses?

2.As you said,I creat the example v_dp_txss1_0 for ZCU102, but there are no pixel remapper mode.

Whrere can i find it?

 

Thanks,

 

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Moderator
Moderator
57 Views
Registered: ‎11-09-2015

Re: dp example av_pat_gen

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HI @gandics 


@gandics wrote:

Hi @florentw ,

As mentioned in topic

https://forums.xilinx.com/t5/Video/tpg-and-dp1-4-IP-not-generating-image/m-p/1016847#M27362

You discuss about replacing tpg with av_pat_gen.

I still have two questions:

1.Could you tell me where can i find the details for dp input changing corresponding to the lane uses?

[Florent] - I do not understand your question. This is controlled by the driver depending on the number of lane trained and the resolution. So you need to control this from the application

2.As you said,I creat the example v_dp_txss1_0 for ZCU102, but there are no pixel remapper mode.

Whrere can i find it?

[Florent] - The reampper IP should be present in the ZCU102 path-through design. It is not required in the DP TX only as the included pattern generator is taking care of sending the data to the correct lanes

Again the pixel remapper is a helper core not available in the catalog. You might want to create your own IP for this.

 

Thanks,

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
58 Views
Registered: ‎11-09-2015

Re: dp example av_pat_gen

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HI @gandics 


@gandics wrote:

Hi @florentw ,

As mentioned in topic

https://forums.xilinx.com/t5/Video/tpg-and-dp1-4-IP-not-generating-image/m-p/1016847#M27362

You discuss about replacing tpg with av_pat_gen.

I still have two questions:

1.Could you tell me where can i find the details for dp input changing corresponding to the lane uses?

[Florent] - I do not understand your question. This is controlled by the driver depending on the number of lane trained and the resolution. So you need to control this from the application

2.As you said,I creat the example v_dp_txss1_0 for ZCU102, but there are no pixel remapper mode.

Whrere can i find it?

[Florent] - The reampper IP should be present in the ZCU102 path-through design. It is not required in the DP TX only as the included pattern generator is taking care of sending the data to the correct lanes

Again the pixel remapper is a helper core not available in the catalog. You might want to create your own IP for this.

 

Thanks,

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
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Registered: ‎05-02-2018

Re: dp example av_pat_gen

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Hi @florentw ,

Thanks for your answer!

I am using DP tx subsystem v2.1 in KC705board.

The question 1,I mean,Is there any documentation explain the choice between the tpg outputs(pixel per clock or data width) and the numbers of DP lane uses?

For example,If I want to use 3840*2160@30Hz with 2 pixel per clock axi4_stream inputting,how many lanes should DP setting?(4lanes@5.4G/2lane@2.7G/.......)And what other settings needed to fit this data format input?

I find out the reampper ip in the ZCU102 path-through design,It is pity that there are no such helper core in KC705.And It is failed to migrate it from ZCU102 to KC705.I have to creat it by myself.

Thanks,

 

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: dp example av_pat_gen

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@gandics wrote:

Hi @florentw ,

Thanks for your answer!

I am using DP tx subsystem v2.1 in KC705board.

The question 1,I mean,Is there any documentation explain the choice between the tpg outputs(pixel per clock or data width) and the numbers of DP lane uses?

For example,If I want to use 3840*2160@30Hz with 2 pixel per clock axi4_stream inputting,how many lanes should DP setting?(4lanes@5.4G/2lane@2.7G/.......)And what other settings needed to fit this data format input?

[Florent] - There are multiple things to take in account. The training with the sink will tell you what you can do or not. Then the driver will try to change this configuration depending on how the system was trained. 

Then your application will be responsible to use this settings to configure the DP input

I find out the reampper ip in the ZCU102 path-through design,It is pity that there are no such helper core in KC705.And It is failed to migrate it from ZCU102 to KC705.I have to creat it by myself.

[Florent] - Once again, this is only to be used in the example design and not supported outside this. The user is expected to write its own IP. So yes, you should write your own.

Thanks,

 

 

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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