UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
584 Views
Registered: ‎10-22-2017

dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

Recently I debugging the K7 board, there is a dp receive interface channel on the board. The displayport rx_ss ip is used. The vivado version used is 2017.4. The phy data width of the dp_rx_ss configuration used is 32, and the dp channel  can receive  dp  video signal correctly.  In order to save resources, the phy data width is configured to 16. But finde that  the dp  channel  cannot be received normally now.
If  use a configuration with a phy data width of 16, what additional operations do i need to do?

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
267 Views
Registered: ‎03-07-2018

Re: dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

Hello @caoshouqi 

Please add following constraints in your 2 Byte KC705 based DP12 example design (TOP_KC705.xdc) to resolve this issue.

create_clock -period 3.703 [get_pins -of [get_cells -hierarchical -filter {name=~*gt*_dp_ss_vid_phy_controller_0_0_gtwrapper_i*gtxe2_i*}] -filter {REF_PIN_NAME == TXOUTCLK}]

create_clock -period 3.703 [get_pins -of [get_cells -hierarchical -filter {name=~*gt*_dp_ss_vid_phy_controller_0_0_gtwrapper_i*gtxe2_i*}] -filter {REF_PIN_NAME == RXOUTCLK}]

You will get critical warnings related to timing does not match for these constraints. You can ignore these warnings.

We have released AR# 72322 for addressing this issue.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------
9 Replies
Xilinx Employee
Xilinx Employee
522 Views
Registered: ‎03-07-2018

Re: dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

Hello @caoshouqi 

In case of 16-bit Video Phy data width perform following checks:

1. Check the RX Initialization Status register (0x0028) and PLL Lock Status (0x0018) register of the Video PHY Controller for Reset done and PLL lock for the active lanes. 

2. Check the 0x43C and 0x440 registers for Symbol_Locked, Channel Equalization and Clock Recovery Done. 

 

Did enabled HDCP option in your design?

HDCP external clock (hdcp_ext_clk) is enabled when HDCP is selected with 16-bit GT interface.

In case of  16-bit GT interface hdcp_ext_clk has to be provided by the user from external MMCM. The frequency requirement of hdcp_ext_clk is rx_lnk_clk/2.

Also Note that lnk_clk = link_rate/20, when GT-Data width is 16-bit. lnk_clk = link_rate/40, when GT-Data width is 32-bit.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Adventurer
Adventurer
507 Views
Registered: ‎10-22-2017

Re: dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

hi@bpatil

Thanks for your replay. 

 I check the log and find that the process is hung at lock the pll clock.  It looks like that the PLL cannot be locked.    The soft code is same, just config phy data width from 32 to 16.  But  the 32 bit configuration is ok.

I add the Two_byte_set function after init  dp_rx_ss. Then the log display that training  is done and the pll is locked , but soon lost. 

The difference between the 32 and 16 I understand is that phy doubles the video clock for dp_rx_ss. Does the SDK also need to modify the control process?

 

 

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
464 Views
Registered: ‎03-07-2018

Re: dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

Hello @caoshouqi 

I have modified KC705 example design (Pass-through without HDCP1.3) DP TX and RX IP phy data width as follows:

EG_RX change.pngEG_TX change.png

I have not performed any changes in Software API of example design (Pass-through without HDCP1.3).

With above mentioned changes, I have successfully run example design with PHY data width = 16 bit on KC705 board with inrevium TB-FMCH-DP3 card. In this case source of DP is Dell T3500 desktop with Nvidia graphics card Quadro FX1800 and Sink for DP is Dell P2415Qb monitor.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Moderator
Moderator
424 Views
Registered: ‎11-09-2015

Re: dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

Hi @caoshouqi ,

Do you have any updates on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Highlighted
Adventurer
Adventurer
409 Views
Registered: ‎10-22-2017

Re: dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

hi@florentw 

Thanks for your reply

The phenomenon I tested here is that under the 16-bit configuration, the speed of 5.4G is not normally received and sent. I have tested it with KC705 and daughter card。

0 Kudos
Moderator
Moderator
403 Views
Registered: ‎11-09-2015

Re: dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

HI @caoshouqi ,

Refer to the design @bpatil mentioned. He was able to run properly with 16-bit data path.

You will need to make sure that you are properly meeting timing in your design


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Adventurer
Adventurer
397 Views
Registered: ‎10-22-2017

Re: dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

hi@florentw 

Thanks for your reply.

@bpatil  has sent his test program to me, I tested the 16-bit configuration pass pass mode does not work properly on the board, when testing the only tx mode with his test program, 2.7G can work normally, 5.4G Cannot display properly.I used the test program generated by example design, and the test results were the same.I don't know why the test results look different.

 

0 Kudos
Xilinx Employee
Xilinx Employee
268 Views
Registered: ‎03-07-2018

Re: dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

Hello @caoshouqi 

Please add following constraints in your 2 Byte KC705 based DP12 example design (TOP_KC705.xdc) to resolve this issue.

create_clock -period 3.703 [get_pins -of [get_cells -hierarchical -filter {name=~*gt*_dp_ss_vid_phy_controller_0_0_gtwrapper_i*gtxe2_i*}] -filter {REF_PIN_NAME == TXOUTCLK}]

create_clock -period 3.703 [get_pins -of [get_cells -hierarchical -filter {name=~*gt*_dp_ss_vid_phy_controller_0_0_gtwrapper_i*gtxe2_i*}] -filter {REF_PIN_NAME == RXOUTCLK}]

You will get critical warnings related to timing does not match for these constraints. You can ignore these warnings.

We have released AR# 72322 for addressing this issue.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------
Adventurer
Adventurer
234 Views
Registered: ‎10-22-2017

Re: dp1.2 rx_ss IP config phy data width from 32 to 16,but the cannot receive dp signal correctly.

Jump to solution

@bpatil 

ok.Bpatil ,thanks for your support.I have test it on kc705 board.After add the constrain, the kc705 board can work normally when config with 2byte.

Thank you very much.

0 Kudos