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Visitor
Visitor
2,701 Views
Registered: ‎06-07-2013

fir decination

I want to decinate from 100MHz data to 80MHz , how to  design . the system clk is 100MHz, resoure data sampling rate is 100MHz, the wanted sampling rate is 80MHZ,fir ip 5.0.

 

can you  attach the design.

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Contributor
Contributor
2,628 Views
Registered: ‎05-13-2013

Re: fir decination

Hi,

 

In the “Filter specification” section of FIR Compile 5.0 select:

-          “Interpolation” as Filter Type

-          “Fixed_Fractional” as Rate  Change Type

-          4 in Interpolation Rate Value

-          5 in Decimation Rate Value

 

Fill the rest of parameters (coefficients, filter architecture... and so on) according to your specifications.

 

Good luck,

IKERLAN FPGA
fpga@ikerlan.es
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