I want to decinate from 100MHz data to 80MHz , how to design . the system clk is 100MHz, resoure data sampling rate is 100MHz, the wanted sampling rate is 80MHZ,fir ip 5.0.
can you attach the design.
In the “Filter specification” section of FIR Compile 5.0 select:
- “Interpolation” as Filter Type
- “Fixed_Fractional” as Rate Change Type
- 4 in Interpolation Rate Value
- 5 in Decimation Rate Value
Fill the rest of parameters (coefficients, filter architecture... and so on) according to your specifications.