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Observer stratix2
Observer
127 Views
Registered: ‎12-21-2018

hdmi tx ss 1080p30 reference clock 4px/clk native video

In my design hdmi tx ss, resolutions from 1080p50 till 4k60 work fine

native video

GTXE2

QPLL

4px/clk

for 1080p30, 1080p25, 1080p24

pixel clock 74.25MHz

reference clock I give is 74.25MHz, when I look into info it says 

         GT status

         ---------

         TX reference clock frequency: 222765056 Hz

so video phy multiplies it by 3

tmds clk is 89,295MHz

then it gives me back tx_video_clk 37,126‬MHz which is pixel clock/2

but in my design it should be pixel clock/4, which is the case with higher resolutions

is it normal? if so how it should work? should I use VIDEO_IN_active_video pin in hdmi_tx_ss as clock enable and not only for active/blanking?

thank you!

UPD:

the differences in phy registers values for 1080p24 and 1080p60:

                             for 1080p24

phy register #24 0x0018 RO PLL Lock Status (PLS)

in dec : 16 in hex : 00000000

phy register #28 0x001C RW TX Initialization (TXI)

in dec : 16843009 in hex : 01010101

GTTXRESET = '1'

phy register #32 0x0020 RO TX Initialization Status (TXIS)

in dec : 394758 in hex : 00060606

TXRESETDONE = '0'

phy register #120 0x0078 RO TX Status (TXS)

in dec : 0 in hex : 00000000

TXPHALIGNDONE = '0'

phy register #524 0x020C RO Transmitter Frequency

in dec : 222765056 in hex : 0D472000

 

                 meanwhile for 1080p60

phy register #24 0x0018 RO PLL Lock Status (PLS)

in dec : 16 in hex : 00000010

qpll

phy register #28 0x001C RW TX Initialization (TXI)

in dec : 0 in hex : 00000000

phy register #32 0x0020 RO TX Initialization Status (TXIS)

in dec : 460551 in hex : 00070707

TXRESETDONE = '1'

phy register #120 0x0078 RO TX Status (TXS)

in dec : 65793 in hex : 00010101

TXPHALIGNDONE = '1'

phy register #524 0x020C RO Transmitter Frequency

in dec : 148510720 in hex : 08DA1800

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1 Reply
Moderator
Moderator
81 Views
Registered: ‎10-04-2017

Re: hdmi tx ss 1080p30 reference clock 4px/clk native video

HI @stratix2,

The clocking in the system is shown below:

In your system because you are using Quad pixels per clock the Video clock is the Pixel clock/4.

When you say the reference clock given is 74.25Mhz, but the core is reporting this  222765056 Hz, this tells me that there is a clocking problem. Either you are actually giving the core 222.7Mhz or the clock running the clock detector has changed(vid_phy_axi4lite_aclk). **The clock detector is responsible for reporting your reference clocks frequency.

Also as a note:

I see that you are in 7-series (GTX)

 

2019-09-19 09_54_01-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

2019-09-19 09_45_55-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

2019-09-19 09_52_18-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

 

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