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Observer michelle
Observer
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Registered: ‎09-29-2018

kcu105 with tpg and dp1.4 IP

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I'm trying to use TPG with Displayport 1.4 on KCU105 and DP1.4 FMC card.

The existing DP example design (zcu102 for tx or rx sst and kcu105 rx to tx pass through), the pattern generation was done through video_pat_gen. It's not an IP available in current library as discussed in this link:

https://forums.xilinx.com/t5/7-Series-FPGAs/DisplayPort-pattern-generator-help/m-p/731769

I'm trying to use TPG IP and DPTX 1.4 IP. Attached is the snapshot of this design. TPG ap_clk and dptxss s_axis_aclk_stream1/tx_vid_clk_stream1 both came from clk_wiz_0/clk_out1. Correct me if this connection has issue.

I have two questions related to the clock:

1. The reference clock clk_in1 to clk_wiz_0 is the 100MHz generated using onboard 300MHz differential clock. This is similar to what zcu102 design example, however I read from xapp1178 (based on kcu709) talks about the vid_clk with link clock as reference. I'm confused here and need confirmation on what reference clock I need to use here.

2. according to dptxss 1.4 product guide, vid_clk should <=150MHz. I thought the vid_ck is pixel clock, maybe it's not. Could you let me know what the relationship is of vid_clk and pixel clock? 

 

Thanks!

Regards,

Michelle

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Moderator
Moderator
238 Views
Registered: ‎11-09-2015

Re: kcu105 with tpg and dp1.4 IP

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HI @michelle,

Yes it can be ok to have the video clock used for the axis interface.

The TPG and the DP s_axis_aclk_stream1 should be connected to the same clock (not only same clock domain)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
270 Views
Registered: ‎11-09-2015

Re: kcu105 with tpg and dp1.4 IP

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Hi @michelle,

1. The xapp1178 is based on the old version of the IP. Please use the example design as reference. I am not sure what clock you are referring as the reference clock. For the clocking between the TPG and the DP IP (i.e. AXI4S clock) you need to use the same clock as s_axi_aclk for the DP. It can be any clock, you just need to make sure it is fast enough for the data

2. The vid_clk is not exactly the pixel clock because sometimes you will transmit up to 4 pixel per clock so the pixel clock is 4 times faster than the vid_clk.

Hope that helps,

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer michelle
Observer
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Registered: ‎09-29-2018

Re: kcu105 with tpg and dp1.4 IP

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Thanks for your response.

The clock reference I referred to is the reference clock to clk_wiz_0 as shown in attached figure. clk_wiz_0 is the one to provide ap_clk for tpg and vid_clk for dp. The input clock I'm using is 100MHz generated by ddr4 using system clk (300MHz). The 100MHz is used for all AXI peripherals except tpg. 

I need clarification of your comment on " For the clocking between the TPG and the DP IP (i.e. AXI4S clock) you need to use the same clock as s_axi_aclk for the DP"

Do you mean the same clock or just the same clock domain?

For DP, there are s_axi_aclk, s_axis_aclk_stream1, tx_vid_clk_stream1. I used 100M axi clock for  s_axi_aclk,  which is also used for the rest AXI peripherals. However, for the other two (aclk_stream and vid_clk), I used the clk_wiz_0 output, which is on the same clock domain as 100M but re-generated to be Pixel_clk/ppc (pixel per clock). Same vid_clk is also connected to tpg ap_clk. Is this OK?

 

Thanks!

Regards,
Michelle

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Moderator
Moderator
239 Views
Registered: ‎11-09-2015

Re: kcu105 with tpg and dp1.4 IP

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HI @michelle,

Yes it can be ok to have the video clock used for the axis interface.

The TPG and the DP s_axis_aclk_stream1 should be connected to the same clock (not only same clock domain)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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