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Contributor
Contributor
625 Views
Registered: ‎06-05-2019

mipi CSI-2 RX ZCU104

Hello, 

I am working with MIPI CSI-2 RX IP. I want to migrate the CSI-2 RX subsystem example design to my ZCU104 FPGA board.

From the schematic of the ZCU104 FPGA board and LI-IMX274MIPI-FMC,  the FMC Pins of MIPI are at 

MIPIC => F17

MIPID0 => L15

MIPID1 => H18

MIPID2 => E18

MIPID3 => J16

However, when i fix the configuration of the CSI-2 RX subsystem, another two ports are automatically generated.

微信截图_20190801212522.png

We can get the information about these new ports in PG232.

微信截图_20190801220914.png

It says that these ports must be connected. But PG232 does not mention how to do it. If these ports stay connected, implementation would encount error as follow.

Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.089 . Memory (MB): peak = 6348.590 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 72bab399
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.156 . Memory (MB): peak = 6348.590 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 6348.590 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-687] Expected cell design_1_i/mipi_csi2_rx_subsystem_0/inst/phy/inst/inst/bd_bf15_phy_0_rx_support_i/slave_rx.bd_bf15_phy_0_rx_hssio_i/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS[13].rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.
ERROR: [Place 30-687] Expected cell design_1_i/mipi_csi2_rx_subsystem_0/inst/phy/inst/inst/bd_bf15_phy_0_rx_support_i/slave_rx.bd_bf15_phy_0_rx_hssio_i/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS[39].rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 5cb32c20
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 6348.590 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 5cb32c20
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 6348.590 ; gain = 0.000
ERROR: [Place 30-99] Placer failed with error: 'Placer initialization failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 2968bdaa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 6348.590 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
238 Infos, 92 Warnings, 7 Critical Warnings and 4 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Thu Aug  1 20:37:58 2019...
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10 Replies
Xilinx Employee
Xilinx Employee
616 Views
Registered: ‎03-30-2016

Re: mipi CSI-2 RX ZCU104

Hello @ivanfan 

You do not need to drive bg*_pin*_nc pins in your RTL design. Leave it as is.
bg*_pin*_nc appears on your IP , because you do not assignment MIPI pins to continuous pins.

Hope this helps
Regards
Leo

Contributor
Contributor
607 Views
Registered: ‎06-05-2019

Re: mipi CSI-2 RX ZCU104

@karnanl

Thank you very much for your timely help. If this is not the reason, then how can I fix the error I encountered in implementation? The log was displayed as follow:

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.089 . Memory (MB): peak = 6348.590 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 72bab399
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.156 . Memory (MB): peak = 6348.590 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 6348.590 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-687] Expected cell design_1_i/mipi_csi2_rx_subsystem_0/inst/phy/inst/inst/bd_bf15_phy_0_rx_support_i/slave_rx.bd_bf15_phy_0_rx_hssio_i/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS[13].rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.
ERROR: [Place 30-687] Expected cell design_1_i/mipi_csi2_rx_subsystem_0/inst/phy/inst/inst/bd_bf15_phy_0_rx_support_i/slave_rx.bd_bf15_phy_0_rx_hssio_i/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS[39].rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 5cb32c20
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 6348.590 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 5cb32c20
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 6348.590 ; gain = 0.000
ERROR: [Place 30-99] Placer failed with error: 'Placer initialization failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 2968bdaa
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 6348.590 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
238 Infos, 92 Warnings, 7 Critical Warnings and 4 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Thu Aug  1 20:37:58 2019...
 

微信截图_20190802112339.png

 

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Xilinx Employee
Xilinx Employee
590 Views
Registered: ‎03-30-2016

Re: mipi CSI-2 RX ZCU104

Hello @ivanfan 

Could you please share your MIPI CSI-2 RX XCI file ?
I will try to re-produce this implementation error.

Thanks
Leo

Contributor
Contributor
580 Views
Registered: ‎06-05-2019

Re: mipi CSI-2 RX ZCU104

@karnanl 

Thank you in advance.

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Xilinx Employee
Xilinx Employee
534 Views
Registered: ‎03-30-2016

Re: mipi CSI-2 RX ZCU104

Hello Ivan @ivanfan 

Thank you for sharing your XCI file.
I will try to test it today.

Thanks
Leo

Highlighted
Xilinx Employee
Xilinx Employee
513 Views
Registered: ‎03-30-2016

Re: mipi CSI-2 RX ZCU104

Hello Ivan @ivanfan 

Thank you for your feedback.

1. Critical warnings in the red-box are reproducible.
    These critical warnings are produced by MIPI DSI TX. It can be safely ignored. Please expect the fix on Vivado 2019.2 or later.
2. Critical warnings in the green-box are also reproducible.
    These critical warnings are produced by HDMI TX IP (since 2018.3 ?!).
    Please ignore for now, fix are scheduled in 2019.2 or later.
3. Orange boxes.
    Unfortunately I cannot reproduce the issue on my side.
    I believe you set incorrect pin assignment on MIPI CSI-2 RX.

    Firstly, could you please try use ZCU102 as a project board ?
    Please try to generate the MIPI Example Design targeting ZCU102.
    After you can confirm that everything are okay. You can change the MIPI D-PHY XDC manually to fit your ZCU104 board connectivity.

The XDC file are something like this:
./design_1_mipi_csi2_rx_subsystem_0_0_ex/design_1_mipi_csi2_rx_subsystem_0_0_ex.srcs/sources_1/bd/design_1/ip/design_1_mipi_csi2_rx_subsystem_0_1/bd_0/ip/ip_2/ip_0/bd_***_phy_0_hssio_rx.xd


Thanks
Leo

XF_MIPI_EXDES_TRIAL.jpg
Moderator
Moderator
469 Views
Registered: ‎11-21-2018

Re: mipi CSI-2 RX ZCU104

Hi @ivanfan 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Contributor
Contributor
453 Views
Registered: ‎06-05-2019

Re: mipi CSI-2 RX ZCU104

Hello @karnanl 

Thank you so much for your help and detailed answer.

Unfortunately, I only have the zcu104 board on hand, and there is no ZCU102 board. I looked at the block design of the zcu104 base trd and found that the two pins are connected to D16 and L20. I made the corresponding changes in my csi project, and passed the synthesis without errors.

 

微信截图_20190815150052.png

微信截图_20190815150204.png

But I encountered another problem while downloading the program. I follow the steps of pg232 to download the program using tcl and get the following results.

 

微信截图_20190815144835.png

微信截图_20190815144852.png

I followed the tutorial searched online to modify the psu_init file and still encountered the same problem.

微信截图_20190815145044.png

Xilinx Employee
Xilinx Employee
416 Views
Registered: ‎03-30-2016

Re: mipi CSI-2 RX ZCU104

Hello Ivan,

Thank you for debugging this.
Yes, have to assigned the bg_pin_nc pins on your device.

Probably this Forum post will helps you on (Mask poll failed at ADDRESS: 0xFD4023E4 MASK: 0x00000010)
Perhaps GTR configuration is not correct.
https://forums.xilinx.com/t5/Embedded-Boot-and-Configuration/Mask-poll-failed-at-ADDRESS-0xFD4023E4-MASK-0x00000010/td-p/941804

If this is not helps, suggest you to post a new question in
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/bd-p/EMBEDDED
https://forums.xilinx.com/t5/Embedded-Boot-and-Configuration/bd-p/EmbBoot

 

Thanks & regards
Leo

Moderator
Moderator
228 Views
Registered: ‎10-04-2017

Re: mipi CSI-2 RX ZCU104

Hi @ivanfan,

Is everything clear for you on this topic?

If your question is answered or your issue is solved, please kindly mark the response which helped find a solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply to the thread giving more information on your current status.

Thanks and Regards,

Don't forget to reply, kudo, and accept as solution.

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