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Voyager
Voyager
1,991 Views
Registered: ‎10-31-2016

mipi CSI-2 RX ZCU106

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Hello, 

 

I am working with MIPI CSI-2 RX IP. Where in the section of pin assignment I find some anomaly. 

 

for sensor LI-IMX274MIPI-FMC V1.1 the FMC Pins of MIPI are at 

MIPID0 => C14

MIPID1 => D8

MIPIC => G6

MIPID2 => G12

MIPID3 => H13

 

From this, if we consider ZCU102 FPGA board then the pin assignment will be as shown below for HPC0. It can be seen that the Nibble and  Byte lanes  are correctly fit:

Capture1.PNG

 

But in the case of ZCU106 HPC0, it is not the case.

 

Capture.PNG

Hence I get an error

[Place 30-687] Expected cell DemoSoftICE_i/mipi_csi2_rx_subsyst_0/U0/phy/inst/bd_718e_phy_0_rx_support_i/slave_rx.bd_718e_phy_0_rx_hssio_i/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS[13].rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.

Please recommend me, how can solve this problem? 

 

Thanking you 

Best regards  

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Xilinx Employee
Xilinx Employee
2,044 Views
Registered: ‎03-30-2016

Re: mipi CSI-2 RX ZCU106

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Hello msh

The table shown here is just an implementation example.

 

Thanks & regards

Leo

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12 Replies
Voyager
Voyager
1,990 Views
Registered: ‎10-31-2016

Re: mipi CSI-2 RX ZCU106

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I forget to add a reference guide for pin assignment, where if the Clock is in T2L then the other pins should be like as shown in the picture. But it is not the case in MIPI block pin assignment for ZCU106 HPC0.

Capture.PNG

 

Also, the HPC1 is not supporting the pin assignment in MIPI IP core. Therefore I cannot use it.

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Moderator
Moderator
1,895 Views
Registered: ‎11-09-2015

Re: mipi CSI-2 RX ZCU106

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Hi @msh,

 

Could you share a test case for this?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Xilinx Employee
Xilinx Employee
1,878 Views
Registered: ‎03-30-2016

Re: mipi CSI-2 RX ZCU106

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Hello @msh

 

Checked the GUI and related document about this.

It seems your claim is correct, and I dont think we have a workaround on this.

 

Are you using ZCU102 based TRD and try to implement it on ZCU106 ? ( If yes, please don't do it since it will not work )

 

Best regards

Leo

 

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Voyager
Voyager
1,835 Views
Registered: ‎10-31-2016

Re: mipi CSI-2 RX ZCU106

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Hi

 

I got TRD for ZCU106 but the fpga chip implemented in this is for something else and I working on xczu7ev-ffvc156-2-e. So I am adapting it. 

 

So far after loading the tcl (after editing) I can see thez have used these setting which Imentioned in the first comment. Therefore it implies that we can use connection saperate from the document. I would request to update the MIPI document as it confuse the developers.

 

Still the project have not start working, so I will update this threat ones it do.

 

Thanks 

Best regards 

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Xilinx Employee
Xilinx Employee
1,726 Views
Registered: ‎03-30-2016

Re: mipi CSI-2 RX ZCU106

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Hello @msh

Thank you for your input.

 

>I would request to update the MIPI document as it confuse the developers.

 

Could you be more specific which part confuses you ?
We can consider that for the next document updates.

 

Thanks
Leo

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Voyager
Voyager
1,717 Views
Registered: ‎10-31-2016

Re: mipi CSI-2 RX ZCU106

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document 
https://www.xilinx.com/support/documentation/ip_documentation/mipi_dphy/v3_1/pg202-mipi-dphy.pdf

 

Page 73. It states that the selection of pins should be as shown, but when I implement the MIPI on ZCU106 board the pins are not in that order. 

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Xilinx Employee
Xilinx Employee
2,045 Views
Registered: ‎03-30-2016

Re: mipi CSI-2 RX ZCU106

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Hello msh

The table shown here is just an implementation example.

 

Thanks & regards

Leo

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Moderator
Moderator
1,650 Views
Registered: ‎11-09-2015

Re: mipi CSI-2 RX ZCU106

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Hello @msh,

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
294 Views
Registered: ‎06-05-2019

Re: mipi CSI-2 RX ZCU106

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Hi @msh 

I try to implement the CSi-2 RX subsystem example design on ZCU104. After I fixed the pin fitted the ZCU104, I encountered the same error you mentioned in this topic. Please recommend me, how did you solve this problem? I am very eager to get your help. Thank you.

 

微信截图_20190801212522.pngthe pins setting

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-687] Expected cell design_1_i/mipi_csi2_rx_subsystem_0/inst/phy/inst/inst/bd_bf15_phy_0_rx_support_i/slave_rx.bd_bf15_phy_0_rx_hssio_i/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS[13].rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.
ERROR: [Place 30-687] Expected cell design_1_i/mipi_csi2_rx_subsystem_0/inst/phy/inst/inst/bd_bf15_phy_0_rx_support_i/slave_rx.bd_bf15_phy_0_rx_hssio_i/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS[39].rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 5cb32c20

 

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Voyager
Voyager
277 Views
Registered: ‎10-31-2016

Re: mipi CSI-2 RX ZCU106

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make sure to connect bg pin (just make right click and creat input pin)

make sure that IO which belong to IO bank of the MIPI all have 1.2V configuration. (consider TRD)

 

the pins configuration you are trying to set is for ZCU106. Hence, you must see what is for ZCU104. 

take camera datasheet, get FMC pins. Then see in FPGA datasheet where these FMC pins are connected i.e. to which FPGA pins. These fpga pins need to be mention in MIPI IP. 

Contributor
Contributor
266 Views
Registered: ‎06-05-2019

Re: mipi CSI-2 RX ZCU106

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Thank you for your timely help.

Because the model of mpsoc in zcu104 and zcu106 are both XCZU7EV-2FFVC1156, the FMC pins confirguation seems to be same in zcu104 and zcu106. I have already reviewed the camera datasheet and zcu104 schematic and the pins configuration should be fitted in the zcu104 board. The I/O constraint displays as follow:

微信截图_20190802151418.png

The voltage setting seems to be corret. But I still encountered errors in implementation.

 

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Voyager
Voyager
264 Views
Registered: ‎10-31-2016

Re: mipi CSI-2 RX ZCU106

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did you connect Bg pins ?

FPGA being same doesnot mean that the pins are connected to same FMC connecting pins (it depend on the evaluation board). I donto know about ZCU104, but if possible do check the zcu104 user guide for fmc pins connection to fpga pins.