05-07-2018 03:55 AM
I am working with MIPI CSI-2 RX IP. Where in the section of pin assignment I find some anomaly.
for sensor LI-IMX274MIPI-FMC V1.1 the FMC Pins of MIPI are at
MIPID0 => C14
MIPID1 => D8
MIPIC => G6
MIPID2 => G12
MIPID3 => H13
From this, if we consider ZCU102 FPGA board then the pin assignment will be as shown below for HPC0. It can be seen that the Nibble and Byte lanes are correctly fit:
But in the case of ZCU106 HPC0, it is not the case.
Hence I get an error
[Place 30-687] Expected cell DemoSoftICE_i/mipi_csi2_rx_subsyst_0/U0/phy/inst/bd_718e_phy_0_rx_support_i/slave_rx.bd_718e_phy_0_rx_hssio_i/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS.rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.
Please recommend me, how can solve this problem?
05-07-2018 03:59 AM
I forget to add a reference guide for pin assignment, where if the Clock is in T2L then the other pins should be like as shown in the picture. But it is not the case in MIPI block pin assignment for ZCU106 HPC0.
Also, the HPC1 is not supporting the pin assignment in MIPI IP core. Therefore I cannot use it.
05-10-2018 02:45 AM
05-10-2018 11:11 PM - edited 05-10-2018 11:12 PM
Checked the GUI and related document about this.
It seems your claim is correct, and I dont think we have a workaround on this.
Are you using ZCU102 based TRD and try to implement it on ZCU106 ? ( If yes, please don't do it since it will not work )
05-13-2018 08:53 AM
I got TRD for ZCU106 but the fpga chip implemented in this is for something else and I working on xczu7ev-ffvc156-2-e. So I am adapting it.
So far after loading the tcl (after editing) I can see thez have used these setting which Imentioned in the first comment. Therefore it implies that we can use connection saperate from the document. I would request to update the MIPI document as it confuse the developers.
Still the project have not start working, so I will update this threat ones it do.
05-23-2018 12:39 AM
Thank you for your input.
>I would request to update the MIPI document as it confuse the developers.
Could you be more specific which part confuses you ?
We can consider that for the next document updates.
05-23-2018 02:56 AM
Page 73. It states that the selection of pins should be as shown, but when I implement the MIPI on ZCU106 board the pins are not in that order.
05-29-2018 02:49 AM
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