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Newbie yayale
Newbie
1,348 Views
Registered: ‎07-12-2018

mipi-CSI-2-rx + AXI4-stream_interconnect ,The data of channel 1 is converted to multiple channels(VC0-VC3)

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A MIPI IP of xilinx was used to receive multichannel camera data;Separate the data according to VC,Into multiple vdma separately. Does axi-streaming-interconnect have this feature that data is then separated directly between mipi-CSI-2-rx and vdma ? Or there are other design methods,Please provide a solution.thanks.

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Contributor
Contributor
1,335 Views
Registered: ‎04-10-2018

Re: mipi-CSI-2-rx + AXI4-stream_interconnect ,The data of channel 1 is converted to multiple channels(VC0-VC3)

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Hello @yayale

If I'm not mistaken, the AXIS-Interconnect has only synchronism and simple logic functionalities as FIFOs and AXIS-Slices, but it is unable to, for example, differentiate video patterns. Generally, the AXIS-Interconnect only redistributes the N inputs to the M outputs.

If you want to separate the Virtual Channel probably you'll need a dedicated logic to do it. I'm not shure if exists an IP which is able to separate it to you.

In the MIPI protocol, the virtual channel has an identifier with 8 bits which has two bits (most significant) to identifies the virtual channel and six to data Type. You can implementate an RTL code which compare this two VC bits and separate it.

 

VC_DI.jpeg

 

VC_Signals.jpeg

 

I taken the images from MIPI CSI-2 Specification

Best Regards

Marcos

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3 Replies
Contributor
Contributor
1,336 Views
Registered: ‎04-10-2018

Re: mipi-CSI-2-rx + AXI4-stream_interconnect ,The data of channel 1 is converted to multiple channels(VC0-VC3)

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Hello @yayale

If I'm not mistaken, the AXIS-Interconnect has only synchronism and simple logic functionalities as FIFOs and AXIS-Slices, but it is unable to, for example, differentiate video patterns. Generally, the AXIS-Interconnect only redistributes the N inputs to the M outputs.

If you want to separate the Virtual Channel probably you'll need a dedicated logic to do it. I'm not shure if exists an IP which is able to separate it to you.

In the MIPI protocol, the virtual channel has an identifier with 8 bits which has two bits (most significant) to identifies the virtual channel and six to data Type. You can implementate an RTL code which compare this two VC bits and separate it.

 

VC_DI.jpeg

 

VC_Signals.jpeg

 

I taken the images from MIPI CSI-2 Specification

Best Regards

Marcos

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Xilinx Employee
Xilinx Employee
1,272 Views
Registered: ‎03-30-2016

Re: mipi-CSI-2-rx + AXI4-stream_interconnect ,The data of channel 1 is converted to multiple channels(VC0-VC3)

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Hello @yayale, Hello @marcos.bissiano

 

@marcos.bissiano is correct that user has to separate the Virtual Channel data by themselves, MIPI IP does not have this features.

 

If your sensor ( or you MIPI TX ) sending MIPI data using multiple Virtual channel, you will see

MIPI CSI-2 RX subsystem toggles video_out_tdest[1:0] , to  identify what Virtual channel data is be transmitted out. ( Note : video_out_tdest[7:2] is a Data type.)

 

So, You can use a single AXI4-stream interconnect to split it into four different stream, by connecting video_out_tdest[1:0] into AXI4-stream interconnect module TDEST input.

( You may want to include tuser / tlast from MIPI IP into tdata if your back-end logic needs this information) 

 

Best regards

Leo

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Moderator
Moderator
1,207 Views
Registered: ‎11-09-2015

Re: mipi-CSI-2-rx + AXI4-stream_interconnect ,The data of channel 1 is converted to multiple channels(VC0-VC3)

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HI @yayale,

 

Did the reply from @marcos.bissiano helped you? If yes, could you kindly mark it as accepted solution (click on accept as solution below the reply while logged in). You might want to also give a kudos (button with the star) to @karnanl to thank him for the clarification.

 

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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