03-12-2019 07:51 AM
I'm trying to use a system ILA to monitor the mipi_phy_if of MIPI CSI-2 RX Subsystem. In the System ILA IP configuration, I select the monitor type to be interface and interface type to be xilinx.com:interface:mipi phy rtl:1.0. But I cannot compile this design because an error pops up in the Design Initialization stage saying: [Opt 31-305] Invalid connectivity on net mipi_phy_if_0_clk_n connected to port mipi_phy_if_0_clk_n. It drives some loads that need a buffer, and other loads that do not need a buffer. This configuration cannot be placed.
Anyone has an idea about this?
03-19-2019 12:09 PM
Please let me know your ILA clock connection details.
Does without ILA, design compiles correctly?
03-20-2019 05:26 AM
The system ILA clock is connected to a 100MHz clock from PS(which is only clock source for the ILA).
The design compiled correctly without ILA.
03-21-2019 04:26 AM
It seems there is some issue with your clock nets.
Please provide post optimized design dcp to check this issue.
I have sent you EZmove package to send your dcp.
03-21-2019 04:32 AM - edited 03-21-2019 04:33 AM
As pointed out by @bpatil in post2, I also suspect there is a problem as to how you are connecting the ILA. Unfortunately you have not shared the ILA connecting info.
Can you please share the info as to how EXACTLY YOU ARE CONNECTING the ILA, so that you get better help?
03-25-2019 02:50 AM
Is "mipi_phy_if_0_clk_n" and "mipi_phy_if_0_clk_p" are the input pin name of your MIPI CSI-2 RX serial clock ?
If the answer is Yes. I don't think this clock signal can be probed using ILA,
since this input clock is directly connected to DPHY_DIFFINBUF buffer module.
Thanks & regards
04-03-2019 08:26 AM
HI @xinyiz ,
Do you have any updates on this? Was one of the replies enough for you?
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