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Observer xinyiz
Observer
304 Views
Registered: ‎09-17-2018

monitor mipi_phy_if signals using system ILA

Hi,

I'm trying to use a system ILA to monitor the mipi_phy_if of MIPI CSI-2 RX Subsystem. In the System ILA IP configuration, I select the monitor type to be interface and interface type to be xilinx.com:interface:mipi phy rtl:1.0. But I cannot compile this design because an error pops up in the Design Initialization stage saying:  [Opt 31-305] Invalid connectivity on net mipi_phy_if_0_clk_n connected to port mipi_phy_if_0_clk_n. It drives some loads that need a buffer, and other loads that do not need a buffer. This configuration cannot be placed.

Anyone has an idea about this?

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6 Replies
Xilinx Employee
Xilinx Employee
252 Views
Registered: ‎03-07-2018

Re: monitor mipi_phy_if signals using system ILA

Hello @xinyiz 

Please let me know your ILA clock connection details.

Does without ILA, design compiles correctly?

Regards,
Bhushan

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Observer xinyiz
Observer
227 Views
Registered: ‎09-17-2018

Re: monitor mipi_phy_if signals using system ILA

The system ILA clock is connected to a 100MHz clock from PS(which is only clock source for the ILA).

The design compiled correctly without ILA.

Xilinx Employee
Xilinx Employee
204 Views
Registered: ‎03-07-2018

Re: monitor mipi_phy_if signals using system ILA

Hello @xinyiz 

It seems there is some issue with your clock nets.

Please provide post optimized design dcp to check this issue.

I have sent you EZmove package to send your dcp.

Regards,
Bhushan

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Scholar dpaul24
Scholar
198 Views
Registered: ‎08-07-2014

Re: monitor mipi_phy_if signals using system ILA

@xinyiz,

As pointed out by @bpatil in post2, I also suspect there is a problem as to how you are connecting the ILA. Unfortunately you have not shared the ILA connecting info.

Can you please share the info as to how EXACTLY YOU ARE CONNECTING the ILA, so that you get better help?

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Xilinx Employee
Xilinx Employee
148 Views
Registered: ‎03-30-2016

Re: monitor mipi_phy_if signals using system ILA

Hello @xinyiz 

Is "mipi_phy_if_0_clk_n" and "mipi_phy_if_0_clk_p" are the input pin name of your MIPI CSI-2 RX serial clock ?

If the answer is Yes. I don't think this clock signal can be probed using ILA,
since this input clock is directly connected to DPHY_DIFFINBUF buffer module.


MIPI_ILA.png

 

Thanks & regards
Leo

Moderator
Moderator
76 Views
Registered: ‎11-09-2015

Re: monitor mipi_phy_if signals using system ILA

HI @xinyiz ,

Do you have any updates on this? Was one of the replies enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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